This article presents a self-powered image sensor with a novel pixel architecture with energy harvesting capabilities. ...

This thesis presents a contribution to the design of readout channels for time-of-flight image sensors. Specifically, the ...

This thesis comprises a set of contributions to the state of the art of embedded computer vision systems. CNNs constitute ...

The demand for sun sensors has skyrocketed in the last years due to the huge expected deployment of satellites associated ...

This paper presents a fully on-chip HV-regulated DC–DC boost converter for the power management unit of an electrical ...

Extracting information of interest from continuous video streams is a strongly demanded computer vision task. For the ...

Esta tesis se centra en el diseño y desarrollo de circuitos integrados (CIs) en tecnologías de fabricación CMOS estándar ...

SPAD stands for Single Photon Avalanche Detectors. SPADs are photodiodes structurally similar to those used in conventional ...

Fotomultiplicador digital de combinación OR de pulsos.El fotomultiplicador comprende un conjunto de macroceldas, cada una ...

A custom system has been developed for medical image acquisition and processing in both the visible and the infrared (IR) ...

A multi-purpose mechanical platform to track moving objects in three-dimensional space has been developed. It is composed ...

Silicon photomultipliers (SiPMs) are arrays of single-photon avalanche diodes (SPADs) connected in parallel. Analog silicon ...

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a ...

This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and ...

El muestreo compresivo (CS) es una teoría de muestreo y una alternativa al proceso de muestreo basado en el teorema de ...

Neuroscience research into how complex brain functions are implemented at cell level requires in vivo neural recording ...

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture ...

This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or ...

Progress in microfabrication technology has opened the way for new possibilities in neuroscience and medicine. Chronic, ...

This thesis presents a contribution to the design of single-photon detectors for medical imaging. Specifically, the focus ...

Los Convertidores de Tiempo a Digital (TDC) son dispositivos que se basan en medir la diferencia entre dos señales de ...

In this paper, we analyze heterogeneous performance exhibited by some popular deep learning software frameworks for visual ...

En este Trabajo de Fin de Máster se ha diseñado un sensor asíncrono con una arquitectura del tipo Time-to-First-Spike ...

In this paper, we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. ...

This article presents PreVIous, a methodology to predict the performance of convolutional neural networks (CNNs) in terms ...

Convolutional Neural Networks (ConvNets) are directed acyclic graphs with node transitions determined by a 1 set of ...

The human brain is the most complex organ in the human body, which consists of approximately 100 billion neurons. These ...

Photon detection at longer wavelengths is much desired for LiDAR applications. Silicon photodiodes with deeper junctions ...

This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural ...

This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends ...

The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the ...

Time-of-flight (ToF) image sensors based on single-photon detection, i.e., SPADs, require some filtering of pixel readings. ...

This paper describes a low-noise, low-power and high dynamic range analog front-end intended for sensing neural signals. ...

This paper presents a sub-μW ac-coupled reconfigurable front-end for the purpose of neural recording. The proposed topology ...

This paper presents a FPGA implementation of a novel depth map estimation algorithm for direct time-of-flight CMOS image ...

This paper describes a multichannel bidirectional front-end for implantable closed-loop neuromodulation. Stimulation ...

While providing the same functionality, the various Deep Learning software frameworks available these days do not provide ...

This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal ...

This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input ...

Sensor de imágenes.El objeto de la invención es un sensor de imágenes (100) con muestreo compresivo "on-chip" para la ...

The spread of event‐driven asynchronous vision sensors during the last years has increased significantly the industrial ...

iCaveats is a Project on the integration of components and architectures for embedded vision in transport and security ...

In this article, we present a review of the driving principles and parameters of a previously reported focal-plane ...

This demo showcases a low-cost smart camera where different hardware configurations can be selected to perform image ...

CMOS image sensors based on single-photon avalanche-diodes (SPAD) are suitable for 2D and 3D vision. Limited by uncorrelated ...

Deep Neural Networks (DNNs) have emerged as the reference processing architecture for the implementation of multiple ...

Single-photon avalanche diodes (SPAD) are photodetectors with exceptional characteristics. This paper proposes a new ...

Compressive sampling allows wrapping the relevant content of an image in a reduced set of data. It exploits the sparsity ...

A spiking pixel to be used in image sensor arrays for asynchronous frame-based operation is presented. The pixel features ...

Compressive sensing (CS) is an alternative to the Shannon limit when the signal to be acquired is known to be sparse or ...

This paper describes a methodology to select the optimum combination of deep neuralnetwork and software framework for ...

We have investigated the capabilities of a customasynchronous spiking image sensor operating in the ...

CMOS Image Sensors (CIS) are key for imaging technol-ogies. These chips are conceived for capturing opticalscenes ...

This live demonstration showcases a cyber-physical system tailored for inexpensive remote bird monitoring. A comprehensive ...

The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a ...

We report a high dynamic range (HDR) image sensor with a linear response that overcomes some of the limitations of sensors ...

Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to ...

La tecnología de tiempo de vuelo se muestra hoy como una muy buena opción para 3D ‘imaging’. Sin embargo, los sensores con ...

This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization ...

Silicon photomultipliers (SiPMs) are meant to substitute photomultiplier tubes in high-energy physics detectors and nuclear ...

This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian pyramid extraction. The ...

Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter ...

This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and ...

This paper shows that the implementation of vision systems benefits from the usage of sensing front-end chips with embedded ...

We present a novel sun sensor concept. It is the very first sun sensor built with an address event representation spiking ...

We present a Tunnel Field-Effect Transistor (TFET)-based pixel circuit for well capacity adjustment that does not require ...

A sun sensor implemented with a spiking pixel matrix is reported. It is the very first one based on an asynchronous ...

This demonstrator reveals the performance and features of a single photon avalanche diode (SPAD) camera prototype. It is ...

This paper addresses a comparison of architectures for the hardware implementation of Gaussian image pyramids. Main ...

TCAD simulations have been conducted on a CMOS image sensor in order to characterize the electrical component of the ...

We present a simple circuit to handle communication between cells of neuromorphic arrays. It allows cells to operate ...

In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised ...

This paper presents a camera prototype for 2D/3D image capture in low illumination conditions based on single-photon ...

A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS ...

A CMOS image sensor architecture that uses a cellular automaton for the pseudo-random compressive sampling matrix generation ...

Esta Tesis presenta arquitecturas, circuitos y chips para el diseño de sensores de visión CMOS con procesamiento paralelo ...

This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization ...

This brief describes a high-dynamic-range technique that compresses wide ranges of illuminations into the available signal ...

The top-down approach to system design allows obtaining separate specifications for each subsystem. In the case of vision ...

The design and measurements of a CMOS pseudodifferential voltage-controlled ring-oscillator (VCRO) are presented. It is ...

La captación de señales neuronales mediante electrodos conectados a circuitos micro-electrónicos es necesaria para ...

Speeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, ...

This letter presents new insights into a high dynamic range (HDR) technique recently reported. We demonstrate that two ...

High dynamic range imaging is central in application fields like surveillance, intelligent transportation and advanced ...

In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is ...

This paper presents a novel event-based vision sensor with two operation modes: intensity mode and spatial contrast ...

This paper presents design principles for reusing charge-redistribution SAR ADCs as digital multipliers. This is illustrated ...

This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical ...

Smart CMOS image sensors can leverage the inherent data-level parallelism and regular computational flow of early vision ...

Image feature extraction is instrumental for most of the best-performing algorithms in computer vision. However, it is ...

Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting ...

We have investigated and compared the performance of photodiodes built with stacked p/n junctions operating in parallel ...

This paper studies the effects of capacitors non-idealities in the performance of un-even split-capacitor SAR ADCs. Also, ...

This demo showcases a High Dynamic Range (HDR) technique recently reported. We demonstrate that two intertwined photodiodes ...

Aiming at designing a CMOS image sensor that combines high fill factor and focal-plane implementation of instrumental image ...

This paper introduces a non-recursive algorithm for motion detection directly from the analysis of compressed samples. The ...

This live demonstration showcases a high dynamic range technique that compresses wide ranges of illuminations into the ...

Sistema (1) de adquisición y transferencia de actividad neuronal que comprende al menos una pluralidad de sensores ...

La presente invención, según se expresa en el enunciado de esta memoria descriptiva, consiste en hardware de señal mixta ...

Compressive sensing is an alternative to Nyquist-rate sampling when the signal to be acquired is known to be sparse or ...

This paper describes a prototype smart imager capable of adjusting the photo-integration time of multiple regions of ...

This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced ...

El algoritmo de Viola-Jones es un método de detección de objetos que se usa ampliamente en la detección de caras en imágenes ...

This demonstration targets the acquisition of realtime video sequences involving High Dynamic Range (HDR) scenes. Adaptation ...

This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone ...

Focal-plane mixed-signal arrays have traditionally been designed according to the general claim that moderate accuracy in ...

This paper investigates the potential of an image sensor that combines event-based asynchronous outputs with conventional ...

The optical characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital ...

This live demonstration showcases the Gaussian pyramid with a CMOS vision sensor. The chip features a 176 120 pixel array ...

The design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital ...

Dispositivo y método para la detección hardware de extremos locales en una imagen que comprende una pluralidad de celdas ...

Accurate generation of picosecond-resolution wide-range time intervals has become a necessity for the characterization of ...

This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26.5 nJ/px at 2.64 Mpx/s, ...

This paper reports a calibration system for automatically adjusting the bandpass and gain characteristics of programmable ...

A single-exposure technique to extend the dynamic range of vision sensors is presented. It is particularly suitable for ...

In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). ...

Advances in electronics, sensor technologies, embedded hardware and software are boosting the application scenarios of ...

While conventional CMOS active pixel sensors embed only the circuitry required for photo-detection, pixel addressing and ...

This paper addresses a CMOS vision sensor with 176 × 120 pixels in standard 0.18 μm CMOS technology that computes the ...

Privacy awareness constitutes a critical aspect for smart camera networks. An ideal awless protection of sensitive information ...

The design of a CMOS image sensor based on single-photon avalanche-diode (SPAD) array with in-pixel time-to-digital converter ...

In computer vision, local descriptors permit to summarize relevant visual cues through feature vectors. These vectors ...

The aim of this article is to guide image sensors designers to optimize the analog-to-digital conversion of pixel outputs. ...

his paper reports an integrated 64-channel neural recording sensor. Neural signals are acquired, filtered, digitized and ...

Privacy concerns are hindering the introduction of smart camera networks in prospective application scenarios like retail ...

The design and characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital ...

CMOS Single Photon Avalanche Diodes (SPADs) are a dedicated type of photodetectors that are attracting increasing interest. ...

The capture, processing and distribution of visual information is one of the major challenges for the paradigm of the ...

This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific ...

This paper presents a low power neural signal amplifier with tunable cut-off frequencies. The presented compact amplifier, ...

This paper draws the attention of the community about the capabilities of an emerging generation of bio-inspired vision ...

This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimummaximum indexing in ...

The design and simulation of a CMOS 8 × 8 single photon avalanche diode (SPAD) array is presented. The chip has been ...

This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a ...

This paper describes a real-time application programmed into Wi-FLIP, a wireless smart camera resulting from the integration ...

This paper presents a 176x144 (QCIF) HDR image sensor where visual information is simultaneously captured and adaptively ...

Esta tesis doctoral es el resultado de un conjunto de trabajos de investigación encaminados a sistematizar y optimizar el ...

This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by an ...

This paper introduces an architecture of a switched-capacitor network for Gaussian pyramid generation. Gaussian pyramids ...

This paper describes the use of a reconfigurable focal-plane processing array in order to achieve an image representation ...

A control and acquisition system for the visualization of the images captured with a High Dynamic Range (HDR) CMOS Image ...

The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the ...

High-speed imagers are required for industrial applications, traffic monitoring, robotics and unmanned vehicles, moviemaking, ...

This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest ...

This paper introduces a two-tier CMOS-3D architecture for generation of Gaussian pyramids, detection of extrema, and ...

This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, ...

This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency ...

Wireless sensor networks constitute a powerful technology particularly suitable for environmental monitoring. With regard ...

This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS ...

This paper presents Wi-FLIP, a vision-enabled WSN node resulting from the integration of FLIP-Q, a prototype vision chip, ...

Vertically integrated focal-plane sensor-processor chip design, combining image sensor with mixed-signal and digital ...

In scale-space filtering signals are represented at several scales, each conveying different details of the original signal. ...

This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane ...

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map ...

This paper describes a real-time application programmed into Wi-FLIP, a wireless smart camera resulting from the integration ...

This chapter describes a 1-D Focal Plane Processor, which has been designed to run continuous-time optical correlation ...

This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth ...

Gaussian filtering is a basic tool for image processing. Noise reduction, scale-space generation or edge detection are ...

This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a selfcalibration ...

Early vision stages represent a considerably heavy computational load. A huge amount of data needs to be processed under ...

The 22 papers in this special issue were originally presented at the 2010 European Solid-State Circuits Conference (ESSCIRC). ...

This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power ...

Single-photon avalanche diodes are compatible with standard CMOS. It means that photo-multipliers for scintillation detectors ...

Incorporating multi-resolution capabilities into imagers renders additional power saving mechanisms in the subsequent image ...

This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by ...

Technological aspects of the 3D integration of a multilayer combined mixed-signal and digital sensor-processor array chip ...

This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This ...

A low power transceiver architecture for the 2.4 GHz ISM band using a 1.0 V supply is presented. It employs a transformer ...

Early detection plays a crucial role to prevent forest fires from spreading. Wireless vision sensor networks deployed ...

This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip ...

This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID ...

This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from ...

This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane ...

This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne ...

This paper presents a prototype vision-enabled sensor node based on a commercial vision system of reduced size and power ...

Compared to other one-step integration methods, the 4th-order Runge-Kutta is much more accurate while still consisting in ...

The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is ...

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with ...

This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital Converter (ADC). The design employs ...

This paper presents a bioinspired integrated tactile coprocessor that is able to generate a warning in the case of slippage ...

Vision is expected to play important roles for car safety enhancement. Imaging systems can be used to enlarging the vision ...

We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by ...

La Electrónica es una disciplina versátil en cuanto a las metodologías y técnicas docentes que pueden emplearse. Frente a ...

This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential ...

This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter ...

Artificial sensitive skins are intended to emulate the human skin to improve the skills of robots and machinery in complex ...

An Electrostatic Discharge (ESD) protected Low- Noise Amplifier (LNA) for the 2.4 GHz ISM band designed in a 0.13 mum ...

This paper presents an accurate and simple model for dc gain nonlinearity of operational amplifiers used in the ...

Portable applications of artificial vision are limited by the fact that conventional processing schemes fail to meet the ...

This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, ...

This paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade ...

This paper presents the design of a continuous-time multibit cascade 2-2-1 sigma-delta modulator for broadband telecom systems.

Time-to-digital converter (TDC) integrated circuit is introduced in this paper. It is based on chain of delay elements ...

This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an ...

The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in ...

This paper presents design techniques to evaluate the noise and distortion of continuous time Gm-C filters. Also presents ...

This paper describes a programmable digital computing architecture dedicated to process information in accordance to the ...

This paper presents design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multi-standard wireless ...

This paper presents a CMOS implementation of a layered CNN concurrent with 32times32 photosensors with locally programmable ...

This paper presents novel double-sampling cascaded sigma-delta modulator topologies for wideband applications. The proposed ...

This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. ...

This paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. ...

This brief presents an efficient method for synthesizing cascaded sigma–delta modulators implemented with continuous-time ...

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under ...

This paper presents a MATLAB® toolbox for the time-domain simulation and high-level sizing of pipeline analog-to-digital ...

This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless ...

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as ...

This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated ...

This paper describes a 0.35-μm CMOS chopper-stabilized switched-capacitor 2-1 cascade ΣΔ modulator for automotive sensor ...

This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential ...

This paper presents a high-level synthesis tool for ΣΔ Modulators (ΣΔMs) that combines an accurate SIMULINK-based time-domain ...

This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber ...

This paper analyses the effect of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero ...

This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's ...

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between ...

This paper presents an efficient method to synthesize cascaded sigma-delta modulators implemented with continuous-time ...

This paper presents a detailed study of the clock jitter error in multibit continuous-time ΣΔ modulators with non-return-to-zero ...

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital ...

This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm ...

This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive ...

The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in ...

Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not ...

This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline ...

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ...

A bioinspired model for mixed-signal array mimics the way in which images are processed in the visual pathway. Focal-plane ...

Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on ...

We introduce a new methodology and experimental implementations for real-time wave-based robot navigation in a complex, ...

This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical ...

This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a ...

This paper presents a MATLAB toolbox for the automated high-level sizing of ΣΔ Modulators (ΣΔMs) based on the combination ...

We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications ...

In this paper, a novel DfT methodology to test high-resolution ΣΔ Modulators (ΣΔM) is introduced. The aim of the proposal ...

Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible ...

This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance ...

From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable ...

The Sigma-Delta Modulator presented in this paper contains a programmable-gain input inferface to accommodate the output ...

Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template ...

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has ...

This paper presents a CMOS 0,6μm mixed-signal MODEM ASIC for data transmission on the low-voltage power line. The circuit ...

An arbitrary order sigma-delta modulator cascude architecture is presented with only I-bit loss of resolution due to scaling ...

The computational cost of transient simulation of /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) at the ...

This paper describes how to extend the capabilities of SIMULINK for the time-domain simulation of /spl Sigma//spl Delta/ ...

This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been ...

This paper describes a full-custom mixed-signal chip that embeds digitally programmable analog parallel processing and ...

This paper describes the design and electrical implementation of a 0.35μm CMOS 17-bit≰0kS/s Sigma-Delta Modulator (ΣΔM) ...

This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay ...

A high-performance Sigma-Delta modulator for wireline communication applications is presenfed It employs a 4th-order cascade ...

The low-level image processing that takes place in the retina is intended to compress the relevant visual information to ...

In this paper, a design approach for the high-level synthesis of programmable continuous-time baseband filters able to ...

This paper presents a CMOS 0.6μm mixed-signal MODEM ASIC for data transmission using the low-voltage power line. This ...

The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow ...

In the central nervous systems of animals like pigeons and locusts, neurons were identified which signal objects approaching ...

Durante las últimas décadas del siglo XX hemos asistido a dos oleadas revolucionarias sucesivas en el ámbito del tratamiento ...

A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the ...

This paper presents a dual-quantization SC Sigma-Delta Modulator intended for A/D Conversion in ADSL applications.

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.

CNN-based analog visual microprocessors have similarities with the so-called Single Instruction Multiple Data systems, ...

This paper explores different trade-offs associated with the design of analog VLSI chips. These trade-offs are related to ...

This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even ...

The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog ...

This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural ...

This paper outlines motivations and models underlying the design of visual microprocessors based on the cellular neural ...

Las Tecnologías de la información y de las Comunicaciones han progresado de forma vertiginosa durante los últimos años. ...

Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically ...

This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level ...

In this paper, an efficient methodology to retargeting and reuse of embedded mixed-signal blocks is presented. Parametrized ...

In this paper, the methodological aspects for the design of mixed-signal map-configurable chaos generators are presented. ...

Ths paper analyses the tonal behaviour of the quantization noise in 2nd-order bandpass SD modulators. The analysis previously ...

This paper presents a detailed study of the effect of the non-linear settling on the harmonic distortion of BandPass SD ...

This paper presents a precise model for the transient behaviour of Fully Differential (FD) SwItched-current (SI) memory ...

We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order ...

This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system ...

In this paper we introduce a novel simulation time bounded behavioral modeling technique that optimally selects the ...

This paper analyses the transient behaviour of SwItched-current (SI) memory cells placed at the front-end of high-speed ...

This paper describes the design of a Sigma-Delta modulator aimed for A/D conversion in xDSL applications, featuring ...

A stored program 2/sup nd/ order/3-layer complex cell cellular neural network Universal Machine (CNN-UM) architecture is ...

We demonstrate the importance of the reconfigurability of a 64/spl times/64 cells size CNN-UM chip. As we show, in such a ...

This paper presents a detailed study on the transient response of SC integrators which takes into account the effects of ...

This paper analyses the tonal behaviour of the quantization noise in second-order bandpass ΣΔ modulators. The analysis ...

We show how a complex object oriented image analysis algorithm can be implemented on a CNNUM chip for video-coding. Besides ...

This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low ...

This paper explores the use of /spl Sigma//spl Delta/ modulators for A/D conversion in xDSL applications. Two high-order ...

This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitallyprogrammable analog ...

This paper presents a CMOS 0.8-/spl mu/m switched-current (SI) fourth-order bandpass /spl Sigma//spl Delta/ modulator ...

This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new ...

Presents a mixed-signal fuzzy controller chip and its application to control of DC motors. The controller is based on a ...

Two Cellular Neural Net Universal Machine (CNN-UM) prototypes are demonstrated in action. The first one is the latest 4096 ...

Demonstrates the processing capabilities of an analog programmable array processor chipMINUS/CNNUC3-which follows the ...

Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, ...

While in most application areas digital processors can solve problems initially, in some fields their capabilities are ...

This paper introduces a new tool which allows the evaluation of different test techniques in a complete impartial manner. ...

In this paper a programmable imager with averaging capabilities will be described which is intended for averaging of ...

This paper introduces a new hierarchical analysis methodology which incorporates approximation strategies during the ...

This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable ...

This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier ...

This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing ...

The use of simplification before generation techniques to enable the approximate symbolic analysis of large analog circuits ...

This paper presents a systematic analysis of the harmonic distortion in SD modulators (SDMs) implemented with fully-differential ...

In this paper, a second order reaction-diffusion equation has been identified which is able to reproduce through parameter ...

We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital progranirnability. This ...

This paper describes ESPRIT 29648, concerning the development of an advanced methodology for the design of a mixed-signal ...

Circuit reduction is a fundamental first step in addressing the symbolic analysis of large analogue circuits. A new algorithm ...

Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements ...

Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided ...

This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the quantization ...

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio ...

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation ...

Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. ...

Learning algorithms have become of great interest to be applied not only to neural or hybrid neuro-fuzzy systems, but also ...

Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually ...

Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision ...

Symbolic analysis potentialities for gaining circuit insight and for efficient repetitive evaluations have been limited ...

Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation ...

This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture ...

Recommendations are given for efficient design of high-frequency /spl Sigma//spl Delta/ modulators using multi-stage ...

Abstract—An electrooptical measurement system for the dc characterization of visible detectors for CMOS-compatible ...

The use of Sigma-Delta (Σ∆) modulation for analog-to-digital conversion (ADC) in the communication frequency range is ...

Behavioral models are used both for top-down design and for bottom-up verification. During top-down design, models are ...

A proposal for an integrated digital communication system using a DCSK chaotic modulation scheme is presented. It is a ...

We present a high-frequency fully-differential current-mode buffer to interface off-chip currents with no significant ...

An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips ...

Fourth-order cascade ΣΔ modulators are very well suited for IC implementation using analog sampled-data circuits because ...

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) ...

This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital ...

This paper addresses the problems arising in the calculation of numerical references (network function coefficients), ...

An operational vision-chip prototype with a wide-range of potential applications in artificial-vision systems is presented. ...

This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). ...

We present a Switched-Current (SI) fourth-order bandpass ΣΔ modulator IC prototype. It uses fully-differential circuits ...

The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to ...

The low/medium precision required for many fuzzy applications makes analog circuits natural candidates to design fuzzy ...

This paper presents an analytical approach to distance term compensation in mismatch models of integrated devices. Firstly, ...

This paper illustrates the use of a CAD methodology to design a high-resolution 2nd-order ZA modulator with optimized power ...

We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications ...

This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) ...

This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic ...

This paper presents two approaches to symbolic analysis of large analog integrated circuits via simplification during the ...

Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular ...

This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the ...

Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about ...

This paper describes a hybrid weight-control strategy for VLSI realizations of programmable Cellular Neural Networks (CNNs), ...

Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates ...

We present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. Its architecture ...

This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state of the art in this field is also studied, pointing out directions for future research.

Fuzzy controllers are able to incorporate knowledge expressed in if-then rules. These rules are given by experts or skilful ...

This paper presents a 2.4 /spl mu/m CMOS IC prototype which includes a programmable chaotic generator and some interface ...

We present a systematic design technique for current-mode piecewise-linear (PWL) function generators. It uses two building ...

In recent years, the technique of simplification during generation has turned out to be very promising for the efficient ...

We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy ...

The Letter reports the first experimental verification of chaotic encryption of audio using custom monolithic chaotic ...

This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fully-differential ...

We present a parallel architecture for fuzzy controllers and a methodology for their realization as analog CMOS chips for ...

Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about ...

This paper reports the first experimental verification of chaotic encryption of audio signals using integrated circuits. ...

This paper reports the first experimental verification of chaotic encryption of audio signals using integrated circuits. ...

This paper presents the use of analog integrated circuits for secure communication based on chaos synchronization. The ...

A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics ...

This paper describes the design of a programmable Cellular Neural Network (CNN) chip, with additional functionalities ...

A tool is presented that evaluates statistical deviations in performance characteristics of analog circuits, starting from ...

This paper focus on the design of adaptive mixed-signal fuzzy chips. These chips have parallel architecture and feature ...

Las aportaciones principales de esta Tesis se refieren al diseño de circuitos electrónicos con las primitivas disponibles ...

Stability and convergency results are reported for a modified continuous-time CNN model. The signal range of the state ...

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...

This communication reports a new modeling of opamp-induced harmonic distortion in SC ΣΔ modulators, which is aimed to ...

The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...

This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component ...

SIRENA is a general simulation environment for artificial neural networks, with emphasis towards CNNs. A special interest ...

This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of ...

A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range ...

Outlines a systematic approach to design fuzzy inference systems using analog integrated circuits in standard CMOS VLSI ...

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. ...

This paper describes a hybrid weight-control strategy for the VLSI realization of programmable CNNs, based on automatic ...

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large ...

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. ...

An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large ...

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS ...

A tool is presented which starting from high level specifications of SC σδ modulators (resolution, bandwidth and oversampling ...

A nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, ...

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular ...

A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. ...

In this paper we will extend the transconductance-mode (T-mode) approach [1] to implement analog continuous-time neural ...

A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization ...

A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial ...

This paper addresses the design of two neural network systems based on the use of pulsing neurons. Each neuron is built ...

A modular analog circuit design approach for hardware implementations of neural networks is presented. This approach is ...

A methodology to design currentmode circuits for piecewise-linear function approximation is presented. The technique is ...

A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order ...

A programmable switched-capacitor circuit for the generation of 1/f/sup y/ noise is reported. The circuit is described by ...

An architecture and related building blocks are presented for the realization of image processing tasks using current-mode ...

A modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. ...

This paper addresses the topic of formula simplification for symbolic analyzers. Previously reported criteria for flat ...

It is shown that using simulated annealing in combination with electrical simulation provides a powerful tool allowing ...

The actual tendency in most of the work that is being done in VLSI neural network research is to use the simplest possible ...

The design of composite opamp Wien-Bridge oscillators is systematically approached by using a general model including ...

A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the ...

In this paper we present a complete VLSI Continuous-Time Bidirectional Associative Memory (BAM). The short term memory ...

A tool for symbolic analysis of analog integrated circuits is presented featuring accurate simplification, pole/zero ...

A frequency tuning circuit is introduced for VCOs (voltage-controlled oscillators) so that the final relationship between ...

Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance ...

Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI ...

A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance ...

Explores the design of cellular neural networks (CNN) by using sampled-data analog current-mode techniques which neither ...

An analog-digital system is presented for the generation of truly random (aperiodic) digital sequences. This model is based ...

An approach to the design of high-frequency monolithic voltage-controlled oscillators using operational transconductance ...

The mathematical neuron basic cells used as basic cells in popular neural network architectures and algorithms are discussed. ...

A CMOS circuit is proposed that emulates FitzHugh-Nagumo's differential equations using OTAs, diode connected MOSFETs and ...

A quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C) is ...

A systematic approach for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated ...

The authors present an accurate nonlinear macromodel of the operational transconductance amplifier (OTA) which is suitable ...

It is shown that the operational transconductance amplifier, as the active element in basic building blocks, can be ...

The suitability of operational transconductance amplifiers (OTAs) as the main active element to obtain basic building ...

An unconventional application of switched-capacitor (SC) circuits is discussed. A systematic method for the design of ...

A programmable analog neural oscillator cell architecture is presented. The proposed neuron circuit is of hysteretic neural ...

A very flexible programmable CMOS analog neural oscillator cell architecture is presented. The proposed neuron circuit ...

A general-purpose nonlinear macromodel for the time-domain simulation of integrated circuit operational amplifiers (op ...

The design of voltage-controlled oscillators (VCOs) using operational transconductance amplifiers (OTAs) is discussed. ...

A circuit for online solving of linear programming problems is presented. The circuit uses switched-capacitor techniques ...

A nonlinear switched-capacitor circuit that generates chaotic signals is reported. The circuit is described by a first-order ...

A special-purpose analog computer made of switched-capacitor circuits is presented for analyzing chaos and bifurcation ...

The applicability of switched-capacitor (SC) components to the design of nonlinear networks is extensively discussed in ...

We report chaotic phenomena observed from a simple nonlinear switched-capacitor circuit. The experimentally measured ...

A new circuit realisation for an analogue switch is reported. The main feature of the proposed design is the low value of ...

A unified treatment of the active compensation for VCVS realized by operational amplifiers is presented. It is a summary ...

A summer amplifier with extended bandwidth is proposed. Compensation of the frequency characteristics is achieved by employing two operational amplifiers instead of external reactive components.