Presentation
A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator
Author/s | Tortosa Navas, Ramón
Aceituno, Antonio Rosa Utrera, José Manuel de la Rodríguez Vázquez, Ángel Benito Fernández Fernández, Francisco Vidal |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2007 |
Deposit Date | 2019-09-05 |
Published in |
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ISBN/ISSN | 1-4244-0921-7/07 |
Abstract | This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by ... This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth. |
Project ID. | TEC2004-01752/MIC |
Citation | Tortosa Navas, R., Aceituno, A., Rosa Utrera, J.M.d.l., Rodríguez Vázquez, Á.B. y Fernández Fernández, F.V. (2007). A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator. En Proceeding of the 2007 International Symposium on Circuits and Systems (ISCAS) (1-4), New Orleans, USA: Institute of Electrical and Electronics Engineers. |
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A 12-bit@40MS s Gm-C Cascade.pdf | 630.1Kb | [PDF] | View/ | |