Ponencia
Practical considerations for the design of cascade multi-bit high-frequency /spl Sigma//spl Delta/ modulators
Autor/es | Medeiro Hidalgo, Fernando
Río Fernández, Rocío del Pérez Verdú, Belén Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1998 |
Fecha de depósito | 2019-10-11 |
Publicado en |
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ISBN/ISSN | 0-7803-5008-1 |
Resumen | Recommendations are given for efficient design of high-frequency /spl Sigma//spl Delta/ modulators using multi-stage (cascade) multi-bit quantization architectures. These cover from pure architectural aspects to cell design ... Recommendations are given for efficient design of high-frequency /spl Sigma//spl Delta/ modulators using multi-stage (cascade) multi-bit quantization architectures. These cover from pure architectural aspects to cell design with special emphasis on the impact of circuit imperfections. Conclusions are validated by measurements on a 13-bit 2.2 MS/s prototype fabricated in a 0.7 /spl mu/m CMOS technology. |
Identificador del proyecto | TIC 97-0580 |
Cita | Medeiro Hidalgo, F., Río Fernández, R.d., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (1998). Practical considerations for the design of cascade multi-bit high-frequency /spl Sigma//spl Delta/ modulators. En 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (161-164), Lisboa, Portugal: Institute of Electrical and Electronics Engineers. |
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