Recent Submissions

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    ACE16K: A 128×128 focal plane analog processor with digital I/O  [Presentation]

    Liñán Cembrano, Gustavo; Rodríguez Vázquez, Ángel Benito; Espejo Meana, Servando Carlos; Domínguez Castro, Rafael (Institute of Electrical and Electronics Engineers, 2002)
    This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The ...
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    A processing element architecture for high-density focal plane analog programmable array processors  [Presentation]

    Liñán Cembrano, Gustavo; Espejo Meana, Servando Carlos; Domínguez Castro, Rafael; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2002)
    The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to ...
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    On the development of a MODEM for data transmission and control of electrical household appliances using the low-voltage power-line  [Presentation]

    Escalera Morón, Sara; Domínguez Matas, Carlos; García González, José Manuel; Guerra Vinuesa, Oscar; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2003)
    This paper presents a CMOS 0,6μm mixed-signal MODEM ASIC for data transmission on the low-voltage power line. The circuit includes all the analog circuitry needed for input interfacing and modulation/demodulation (PLL-based ...
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    A versatile sensor interface for programmable vision systems-on-chip  [Presentation]

    Rodríguez Vázquez, Ángel Benito; Liñán Cembrano, Gustavo; Roca Moreno, Elisenda; Espejo Meana, Servando Carlos; Domínguez Castro, Rafael (The International Society for Optical Engineering - SPIE, 2003)
    This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35μm n-well CMOS technology with one poly layer and five ...
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    Programmable retinal dynamics in a CMOS mixed-signal array processor chip  [Presentation]

    Carmona Galán, Ricardo; Jiménez Garrido, Francisco José; Domínguez Castro, Rafael; Espejo Meana, Servando Carlos; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2003)
    The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully ...
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    CMOS mixed-signal MODEM for data transmission and control of electrical household appliances using the low-voltage power-line  [Presentation]

    Escalera Morón, Sara; Domínguez Matas, Carlos; García González, José Manuel; Guerra Vinuesa, Oscar; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2003)
    This paper presents a CMOS 0.6μm mixed-signal MODEM ASIC for data transmission using the low-voltage power line. This circuit includes all the analog blocks needed for input interfacing and modulation/demodulation (PLL-based ...
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    A ΣΔ modulator for a programmable-gain, low-power, high-linearity automotive sensor interface  [Presentation]

    Rosa Utrera, José Manuel de la; Medeiro Hidalgo, Fernando; Pérez Verdú, Belén; Río Fernández, Rocío del; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2003)
    This paper describes the design and electrical implementation of a 0.35μm CMOS 17-bit≰0kS/s Sigma-Delta Modulator (ΣΔM) forming part of a sensor interface for automotive applications. First of all, the paper discusses the ...
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    A mixed-signal early vision chip with embedded image and programming memories and digital I/O  [Presentation]

    Liñán Cembrano, Gustavo; Rodríguez Vázquez, Ángel Benito; Domínguez Castro, Rafael; Espejo Meana, Servando Carlos (The International Society for Optical Engineering - SPIE, 2003)
    From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS ...
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    System-level optimization of baseband filters for communication applications  [Presentation]

    Fernández Bootello, Juan Francisco; Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2003)
    In this paper, a design approach for the high-level synthesis of programmable continuous-time baseband filters able to achieve optimum trade-off among dynamic range, distortion behavior, mismatch tolerance and power area ...
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    A Reuse-based framework for the design of analog and mixed-signal ICs  [Presentation]

    Castro López, Rafael; Fernández Fernández, Francisco Vidal; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering -SPIE, 2005)
    Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping ...
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    ACE 16k based stand-alone system for real-time pre-processing tasks  [Presentation]

    Carranza González, Luis; Jiménez Garrido, Francisco José; Liñán Cembrano, Gustavo; Roca Moreno, Elisenda; Espejo Meana, Servando Carlos; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2005)
    This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ...
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    A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization  [Presentation]

    Guerra Vinuesa, Oscar; Escalera Morón, Sara; Rosa Utrera, José Manuel de la; Medeiro Hidalgo, Fernando; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2005)
    This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator ...
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    Tactile on-chip pre-processing with techniques from artificial retinas  [Presentation]

    Maldonado López, Rocío; Vidal Verdú, Fernando; Liñán Cembrano, Gustavo; Roca Moreno, Elisenda; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2005)
    The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in tele-presence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide ...
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    Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK  [Presentation]

    Ruiz Amaya, Jesús; Rosa Utrera, José Manuel de la; Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2005)
    This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded ...
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    Geometrically-constrained, parasitic-aware synthesis of analog ICs  [Presentation]

    Castro López, Rafael; Fernández Fernández, Francisco Vidal; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2005)
    In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced ...
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    Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study  [Presentation]

    Tortosa Navas, Ramón; Rosa Utrera, José Manuel de la; Rodríguez Vázquez, Ángel Benito; Fernández Fernández, Francisco Vidal (The International Society for Optical Engineering - SPIE, 2005)
    This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have ...
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    On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis  [Presentation]

    Castro López, Rafael; Fernández Fernández, Francisco Vidal; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2005)
    Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. ...
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    Locust-inspired vision system on chip architecture for collision detection in automotive applications  [Presentation]

    Carranza González, Luis; Laviana, Rubén; Vargas Sierra, Sonia; Cuadri Carvajo, Jorge; Liñán Cembrano, Gustavo; Roca Moreno, Elisenda; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2006)
    This paper describes a programmable digital computing architecture dedicated to process information in accordance to the organization and operating principles of the four-layer neuron structure encountered at the visual ...
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    A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter  [Presentation]

    Fernández Bootello, Juan Francisco; Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering- SPIE, 2005)
    This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra's series theory and matrix algebra manipulation. ...
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    CMOS Architectures and circuits for high-speed decision-making from image flows  [Presentation]

    Rodríguez Vázquez, Ángel Benito; Domínguez Castro, Rafael; Jiménez Garrido, Francisco José; Morillas Castillo, Sergio; Listán, Juan; Alba, Luis; Utrera, Cayetana; Romay Juárez, Rafael; Medeiro Hidalgo, Fernando (The International Society for Optical Engineering (SPIE), 2008)
    We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by exploiting bio-inspiration and performing processing tasks in parallel manner and concurrently with image ...

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