Now showing items 1-5 of 5
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm [Article]
(Institute of Electrical and Electronics Engineers, 2011)
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the ...
MOST moderate-weak-inversion region as the optimum design zone for CMOS 2.4-GHz CS-LNAs [Article]
(Institute of Electrical and Electronics Engineers, 2014)
In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption ...
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs [Article]
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design ...
Design Methodology for Face Detection Acceleration [Presentation]
(Institute of Electrical and Electronics Engineers, 2013)
A design methodology to accelerate the face detection for embedded systems is described, starting from high level (algorithm optimization) and ending with low level (software and hardware codesign) by addressing the ...
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits [Article]
(Institute of Electrical and Electronics Engineers, 2009)
We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the ...