Now showing items 1-20 of 303

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      1.2V, 1.96mW @ 2.4GHz CMOS-90nm switched-transconductor mixer  [Presentation]

      Villegas Calvo, José Alberto; Vázquez García de la Vega, Diego; Rueda Rueda, Adoración (2010)
      This paper presents the design of a fully differential double balanced switched transconductor mixer for ZigBee applications in the 2.4GHz band. It provides programmable conversion gain by using an active load stage. ...
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      1/f/sup y/ noise generation through a chaotic nonlinear switched-capacitor circuit  [Presentation]

      Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1992)
      A programmable switched-capacitor circuit for the generation of 1/f/sup y/ noise is reported. The circuit is described by a chaotic first-order piecewise-linear finite-difference equation which yields a hopping transition ...
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      1D Cellular Automata for Pulse Width Modulated Compressive Sampling CMOS Image Sensors  [Presentation]

      Trevisi, Marco; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2018)
      Compressive sensing (CS) is an alternative to the Shannon limit when the signal to be acquired is known to be sparse or compressible in some domain. Since compressed samples are non-hierarchical packages of information, ...
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      3-Layer CNN Chip for Focal-Plane Complex Dynamics with Adaptive Image Capture  [Presentation]

      Domínguez Matas, Carlos; Carmona Galán, Ricardo; Sánchez Fernández, Francisco J.; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2006)
      This paper presents a CMOS implementation of a layered CNN concurrent with 32times32 photosensors with locally programmable integration time for adaptive image capture. The network is arranged in two layers containing ...
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      3D multi-layer vision architecture for surveillance and reconnaissance applications  [Presentation]

      Földesy, Péter; Carmona Galán, Ricardo; Zarandy, A.; Rekeczky, Csaba; Rodríguez Vázquez, Ángel Benito; Roska, Tamás (Institute of Electrical and Electronics Engineers, 2009)
      The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is ...
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      5×5 SPAD matrices for the study of the trade-offs between fill factor, dark count rate and crosstalk in the design of CMOS image sensors  [Presentation]

      Moreno García, Manuel; Río Fernández, Rocío del; Guerra Vinuesa, Oscar; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2014)
      CMOS Single Photon Avalanche Diodes (SPADs) are a dedicated type of photodetectors that are attracting increasing interest. Crosstalk and fill factor are magnitudes that become important when dealing with arrays of SPADs. ...
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      A 0.13μm CMOS current steering D/A converter for PLC and VDSL applications  [Presentation]

      Ruiz Amaya, Jesús; Fernández Bootello, Juan Francisco; Rosa Utrera, José Manuel de la; Delgado Restituto, Manuel ; Río Fernández, Rocío del (2005)
      This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification ...
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      A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter  [Presentation]

      Fernández Bootello, Juan Francisco; Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering- SPIE, 2005)
      This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra's series theory and matrix algebra manipulation. ...
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      A 0.18μm CMOS low-noise elliptic low-pass continuous-time filter  [Presentation]

      Fernández Bootello, Juan Francisco; Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2005)
      This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline communication receiver. As an additional attribute, the filter provides programmable boost in the pass-band ...
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      A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization  [Presentation]

      Guerra Vinuesa, Oscar; Escalera Morón, Sara; Rosa Utrera, José Manuel de la; Medeiro Hidalgo, Fernando; Rodríguez Vázquez, Ángel Benito (The International Society for Optical Engineering - SPIE, 2005)
      This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator ...
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      A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator  [Presentation]

      García González, José Manuel; Escalera Morón, Sara; Rosa Utrera, José Manuel de la; Guerra Vinuesa, Oscar; Medeiro Hidalgo, Fernando; Río Fernández, Rocío del; Pérez Verdú, Belén; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2004)
      This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35μm standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier ...
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      A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing  [Presentation]

      Carmona Galán, Ricardo; Espejo Meana, Servando Carlos; Domínguez Castro, Rafael; Rodríguez Vázquez, Ángel Benito; Roska, Tamás; Kozek, Tibor; Chua, Leon O. (Institute of Electrical and Electronics Engineers, 1998)
      An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor ...
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      A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator  [Presentation]

      Tortosa Navas, Ramón; Aceituno, Antonio; Rosa Utrera, José Manuel de la; Rodríguez Vázquez, Ángel Benito; Fernández Fernández, Francisco Vidal (Institute of Electrical and Electronics Engineers, 2007)
      This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by ...
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      A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology  [Presentation]

      Río Fernández, Rocío del; Medeiro Hidalgo, Fernando; Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Rodríguez Vázquez, Ángel Benito (2000)
      This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, ...
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      A 16 Rules@2.5Mflips Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip  [Presentation]

      Vidal Verdú, Fernando; Navas González, Rafael; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 1996)
      We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy inferences per second) with 8.6mW power consumption. It occupies 2.89mm 2 (including pads) in a CMOS 1μm ...
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      A 2.2 μW analog front-end for multichannel neural recording  [Presentation]

      Valtierra, José Luis; Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2017)
      In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised by a two-stage AC-coupled low-noise amplifier (LNA) and a one stage AC-coupled variable gain ...
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      A 2.5-V CMOS Wideband Sigma-Delta Modulator  [Presentation]

      Río Fernández, Rocío del; Medeiro Hidalgo, Fernando; Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2003)
      A high-performance Sigma-Delta modulator for wireline communication applications is presenfed It employs a 4th-order cascade multi-bit architecfure that requires only 16 oversampling ratio, and has been implemented using ...
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      A 2.5-V ΣΔ modulator in 0.25-um CMOS for ADSL  [Presentation]

      Río Fernández, Rocío del; Medeiro Hidalgo, Fernando; Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2002)
      This paper presents a dual-quantization SC Sigma-Delta Modulator intended for A/D Conversion in ADSL applications.
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      A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications  [Presentation]

      Villegas Calvo, José Alberto; Fiorelli Martegani, Rafaella Bianca; Ginés Arteaga, Antonio José; Doldan Lorenzo, Ricardo; Jalón, Maria Ángeles; Acosta Jiménez, Antonio José; Peralías Macías, Eduardo; Vázquez García de la Vega, Diego (2008)
      This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The ...
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      A 26.5 nJ/px 2.64 Mpx/s CMOS Vision Sensor for Gaussian Pyramid Extraction  [Presentation]

      Suárez, Manuel; Fernández Berni, Jorge; Carmona Galán, Ricardo; Cabello, D.; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2014)
      This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions employing an imager and a separate digital processor. ...