Ponencia
3D multi-layer vision architecture for surveillance and reconnaissance applications
Autor/es | Földesy, Péter
Carmona Galán, Ricardo Zarandy, A. Rekeczky, Csaba Rodríguez Vázquez, Ángel Benito Roska, Tamás |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2009 |
Fecha de depósito | 2019-09-06 |
Publicado en |
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ISBN/ISSN | 978-1-4244-3896-9 978-1-4244-3896-9 |
Resumen | The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is ... The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is integrated via bump bonding technology. The chip is constructed of a 320 x 240 sensor array layer, closely coupled with a 160 x 120 mixed-signal processor array layer, a digital frame buffer layer, and an 8 x 8 digital fovea processor array layer. The chip is designed to solve image registration and feature extraction above 1000FPS. |
Identificador del proyecto | N00173-08-C-4005 |
Cita | Földesy, P., Carmona Galán, R., Zarandy, A., Rekeczky, C., Rodríguez Vázquez, Á.B. y Roska, T. (2009). 3D multi-layer vision architecture for surveillance and reconnaissance applications. En European Conference on Circuit Theory and Design (185-188), Antalya, Turquia: Institute of Electrical and Electronics Engineers. |
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