3D multi-layer vision architecture for surveillance and reconnaissance applications

Földesy, Péter; Carmona Galán, Ricardo; Zarandy, A.; Rekeczky, Csaba; Rodríguez Vázquez, Ángel Benito; Roska, Tamás

doi:10.1109/ECCTD.2009.5274944

Ponencia

dc.creator	Földesy, Péter	es
dc.creator	Carmona Galán, Ricardo	es
dc.creator	Zarandy, A.	es
dc.creator	Rekeczky, Csaba	es
dc.creator	Rodríguez Vázquez, Ángel Benito	es
dc.creator	Roska, Tamás	es
dc.date.accessioned	2019-09-06T13:36:01Z
dc.date.available	2019-09-06T13:36:01Z
dc.date.issued	2009
dc.identifier.citation	Földesy, P., Carmona Galán, R., Zarandy, A., Rekeczky, C., Rodríguez Vázquez, Á.B. y Roska, T. (2009). 3D multi-layer vision architecture for surveillance and reconnaissance applications. En European Conference on Circuit Theory and Design (185-188), Antalya, Turquia: Institute of Electrical and Electronics Engineers.
dc.identifier.isbn	978-1-4244-3896-9	es
dc.identifier.issn	978-1-4244-3896-9	es
dc.identifier.uri	https://hdl.handle.net/11441/89034
dc.description.abstract	The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is integrated via bump bonding technology. The chip is constructed of a 320 x 240 sensor array layer, closely coupled with a 160 x 120 mixed-signal processor array layer, a digital frame buffer layer, and an 8 x 8 digital fovea processor array layer. The chip is designed to solve image registration and feature extraction above 1000FPS.	es
dc.description.sponsorship	Office of Naval Research (USA) N00173-08-C-4005	es
dc.format	application/pdf	es
dc.language.iso	eng	es
dc.publisher	Institute of Electrical and Electronics Engineers	es
dc.relation.ispartof	European Conference on Circuit Theory and Design (2009), p 185-188
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.title	3D multi-layer vision architecture for surveillance and reconnaissance applications	es
dc.type	info:eu-repo/semantics/conferenceObject	es
dcterms.identifier	https://ror.org/03yxnpp24
dc.type.version	info:eu-repo/semantics/acceptedVersion	es
dc.rights.accessRights	info:eu-repo/semantics/openAccess	es
dc.contributor.affiliation	Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo	es
dc.relation.projectID	N00173-08-C-4005	es
dc.relation.publisherversion	http://dx.doi.org/10.1109/ECCTD.2009.5274944	es
dc.identifier.doi	10.1109/ECCTD.2009.5274944	es
idus.format.extent	4 p.	es
dc.publication.initialPage	185	es
dc.publication.endPage	188	es
dc.eventtitle	European Conference on Circuit Theory and Design	es
dc.eventinstitution	Antalya, Turquia	es
dc.identifier.sisius	5436242	es

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