Ponencia
Architectures and building blocks for CMOS VLSI analog "neural" programmable optimizers
Autor/es | Domínguez Castro, Rafael
Rodríguez Vázquez, Ángel Benito Huertas Díaz, José Luis Sánchez Sinencio, Edgar |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1992 |
Fecha de depósito | 2020-03-13 |
Publicado en |
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ISBN/ISSN | 0-7803-0593-0 0271-4310 |
Resumen | A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization algorithms with digital programmability of the problem weights. Area overhead due to programmability ... A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization algorithms with digital programmability of the problem weights. Area overhead due to programmability is reduced by using a time multiplexing methodology. It allows all the weights of each multiple inputs processing unit to be digitally-controlled by just using one weighted component array. The proposed architecture is very well suited for MOS VLSI realization using Switched-Capacitor (SC) techniques. SC schematics for the different building blocks are presented and demonstrated via empirical results. |
Cita | Domínguez Castro, R., Rodríguez Vázquez, Á.B., Huertas Díaz, J.L. y Sánchez Sinencio, E. (1992). Architectures and building blocks for CMOS VLSI analog neural programmable optimizers. En IEEE International Symposium on Circuits and Systems (1525-1528), San Diego, USA: Institute of Electrical and Electronics Engineers. |
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