Artículo
Equalization-Based Digital Background Calibration Technique for Pipelined ADCs
Autor/es | Zeinali, Behzad
Moosazadeh, Tohid Yavari, Mohammad Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2014 |
Fecha de depósito | 2019-12-10 |
Publicado en |
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Resumen | In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured ... In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC. |
Cita | Zeinali, B., Moosazadeh, T., Yavari, M. y Rodríguez Vázquez, Á.B. (2014). Equalization-Based Digital Background Calibration Technique for Pipelined ADCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (2), 322-333. |
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