Ponencia
ACE16K: A 128×128 focal plane analog processor with digital I/O
Autor/es | Liñán Cembrano, Gustavo
Rodríguez Vázquez, Ángel Benito Espejo Meana, Servando Carlos Domínguez Castro, Rafael |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2002 |
Fecha de depósito | 2020-01-31 |
Publicado en |
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ISBN/ISSN | 981-238-121-X |
Resumen | This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The ... This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The chip has been designed to achieve the high-speed and moderate-accuracy (8b) requirements of most real time early-vision processing applications. It is easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 90% of them working in analog mode, and exhibits a relatively low power consumption-<4 W, i.e. less than 1 μW per transistor. Computing vs. power peak values are in the order of 1 TeraOPS/W, while maintained VGA processing throughputs of 100 frames/s are possible with about 10-20 basic image processing tasks on each frame. |
Cita | Liñán Cembrano, G., Rodríguez Vázquez, Á.B., Espejo Meana, S.C. y Domínguez Castro, R. (2002). ACE16K: A 128×128 focal plane analog processor with digital I/O. En 7th IEEE International Workshop on Cellular Neural Networks and Their Applications (132-139), Frankfurt, Alemania: Institute of Electrical and Electronics Engineers. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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ACE16K A 128x128 FOCAL PLANE.pdf | 275.4Kb | [PDF] | Ver/ | |