Artículo
Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology
Autor/es | Medeiro Hidalgo, Fernando
Pérez Verdú, Belén Rosa Utrera, José Manuel de la Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1997 |
Fecha de depósito | 2018-07-24 |
Publicado en |
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Resumen | This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an ... This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16.4 bit at a digital output rate of 9.6 kHz with a power consumption of 1.7 mW. It yields a value of Power(W)/[2^resolution(bit) * Outpur rate(Hz)] which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies. |
Cita | Medeiro Hidalgo, F., Pérez Verdú, B., Rosa Utrera, J.M.d.l. y Rodríguez Vázquez, Á.B. (1997). Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology. Journal Circuit Theory Applications, 25 (5), 319-334. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Using CAD Tools for Shortening.pdf | 1.546Mb | [PDF] | Ver/ | |