Artículo
A 3-D Chip Architecture for Optical Sensing and Concurrent Processing
Autor/es | Rodríguez Vázquez, Ángel Benito
Carmona Galán, Ricardo Domínguez Matas, Carlos Suárez Cambre, Manuel Brea Sánchez, Víctor Manuel Pozas, Francisco Liñán Cembrano, Gustavo Foldessy, Peter Zarandy, Akos Rekeczky, Csaba |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2010 |
Fecha de depósito | 2019-08-12 |
Publicado en |
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Resumen | This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture
employs the multi-functional pixel concept to achieve full parallel processing of the information ... This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer, consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5μm x 5μm pitch. |
Identificador del proyecto | 2006-TIC-2352. |
Cita | Rodríguez Vázquez, Á.B., Carmona Galán, R., Domínguez Matas, C., Suárez Cambre, M., Brea Sánchez, V.M., Pozas, F.,...,Rekeczky, C. (2010). A 3-D Chip Architecture for Optical Sensing and Concurrent Processing. Proceedings of SPIE, 7726, 772613. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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772613.pdf | 5.784Mb | [PDF] | Ver/ | |