Presentation
A novel CMOS analog neural oscillator cell
Author/s | Linares Barranco, Bernabé
Sánchez Sinencio, Edgar Newcomb, Robert W. Rodríguez Vázquez, Ángel Benito ![]() ![]() ![]() ![]() ![]() ![]() ![]() Huertas Díaz, José Luis |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Date | 1989 |
Published in |
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Abstract | A very flexible programmable CMOS analog neural oscillator cell architecture is presented. The proposed neuron circuit architecture is a hysteretic neural-type pulse oscillator. Its implementation consists of a transconductance ... A very flexible programmable CMOS analog neural oscillator cell architecture is presented. The proposed neuron circuit architecture is a hysteretic neural-type pulse oscillator. Its implementation consists of a transconductance comparator, a capacitor, and two nonlinear resistors. It has over nine decades of oscillation frequency range, i.e., from 10/sup -2/ Hz to 20 MHz. This range has been experimentally verified. The oscillator cell in the test chip was implemented in a standard 3- mu m (p-well), double-metal CMOS technology and has a dimension of about 44000 mu m/sup 2/ (without the capacitor). Preliminary measurements and simulated results agree very well. |
Citation | Linares Barranco, B., Sánchez Sinencio, E., Newcomb, R.W., Rodríguez Vázquez, Á.B. y Huertas Díaz, J.L. (1989). A novel CMOS analog neural oscillator cell. En IEEE International Symposium on Circuits and Systems (ISCAS) (794-797), Portland, USA: Institute of Electrical and Electronics Engineers. |
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A NOVEL CMOS ANALOG NEURAL.pdf | 353.3Kb | ![]() | View/ | |