Presentation
A prototype tool for optimum analog sizing using simulated annealing
| Author/s | Medeiro Hidalgo, Fernando
Domínguez Castro, Rafael Rodríguez Vázquez, Ángel Benito 
Huertas Díaz, José Luis |
| Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
| Date | 1992 |
| Published in |
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| ISBN/ISSN | 0-7803-0593-0 0271-4310 |
| Abstract | It is shown that using simulated annealing in combination with electrical simulation provides a powerful tool allowing unexperienced designer to size complex analogue building blocks starting from scratch. A cost function ... |
| Citation | Medeiro Hidalgo, F., Domínguez Castro, R., Rodríguez Vázquez, Á.B. y Huertas Díaz, J.L. (1992). A prototype tool for optimum analog sizing using simulated annealing. En IEEE International Symposium on Circuits and Systems (1933-1936), San Diego, USA: Institute of Electrical and Electronics Engineers. |
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| Files | Size | Format | View | Description |
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| A prototype tool for optimum ... | 309.1Kb | 
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https://hdl.handle.net/11441/94147
https://doi.org/10.1109/ISCAS.1992.230431This item appears in the following collection(s)
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