Ponencia
ToF Estimation Based on Compressed Real-Time Histogram Builder for SPAD Image Sensors
Autor/es | Vornicu, Ion
Darie, Ángela Carmona Galán, Ricardo Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2019 |
Fecha de depósito | 2019-12-13 |
Publicado en |
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ISBN/ISSN | 978-1-7281-0397-6 2158-1525 |
Resumen | This paper presents a FPGA implementation of a novel depth map estimation algorithm for direct time-of-flight CMOS image sensors (dToF-CISs) based on single-photon avalanche-diodes (SPADs). Conventional ToF computation ... This paper presents a FPGA implementation of a novel depth map estimation algorithm for direct time-of-flight CMOS image sensors (dToF-CISs) based on single-photon avalanche-diodes (SPADs). Conventional ToF computation algorithms rely on complete ToF histograms. The next generation of high speed dToF-CIS is expected to have wide dynamic range and high depth resolution. Applications such as 3D imaging based on dToF-CISs require pixel-level ToF histograms which have to be stored by huge fully-random access memory (RAM) modules. The proposed shifted inter-frame histogram (SiFH) algorithm has the same accuracy but requires a memory footprint 128 times smaller than the conventional algorithm. Thus a much larger number of pixels can be resolved using limited block RAM resources of FPGAs. Moreover the overall frame rate is also remarkably improved compared to the scanning method. The proof of concept of the SiFH algorithm on 15 bits has been implemented on Spartan-3E. An automated testbench was developed to confirm that no ambiguity errors occur along the entire dynamic range. |
Identificador del proyecto | N00014-19-1-2156
TEC2015-66878-C3-1-R TIC 2338- 2013 |
Cita | Vornicu, I., Darie, Á., Carmona Galán, R. y Rodríguez Vázquez, Á.B. (2019). ToF Estimation Based on Compressed Real-Time Histogram Builder for SPAD Image Sensors. En IEEE International Symposium on Circuits and Systems (ISCAS) (8702361-), Sapporo. Japón: Institute of Electrical and Electronics Engineers. |
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