Ponencia
Robust symmetric multiplication for programmable analog VLSI array processing
Autor/es | Domínguez Matas, Carlos
Carmona Galán, Ricardo Sánchez Fernández, Francisco J. Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2006 |
Fecha de depósito | 2020-04-15 |
Publicado en |
|
ISBN/ISSN | 1-4244-0394-4 |
Resumen | This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several ... This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs. |
Identificador del proyecto | N-00014- 02-1-0884
TIC2003-09817-C02-01 |
Cita | Domínguez Matas, C., Carmona Galán, R., Sánchez Fernández, F.J. y Rodríguez Vázquez, Á.B. (2006). Robust symmetric multiplication for programmable analog VLSI array processing. En 13th IEEE International Conference on Electronics, Circuits and Systems (1332-1335), Niza, Francia: Institute of Electrical and Electronics Engineers. |
Ficheros | Tamaño | Formato | Ver | Descripción |
---|---|---|---|---|
Robust Symmetric Multiplication ... | 197.7Kb | [PDF] | Ver/ | |