dc.creator | Domínguez Matas, Carlos | es |
dc.creator | Carmona Galán, Ricardo | es |
dc.creator | Sánchez Fernández, Francisco J. | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.date.accessioned | 2020-04-15T13:57:14Z | |
dc.date.available | 2020-04-15T13:57:14Z | |
dc.date.issued | 2006 | |
dc.identifier.citation | Domínguez Matas, C., Carmona Galán, R., Sánchez Fernández, F.J. y Rodríguez Vázquez, Á.B. (2006). Robust symmetric multiplication for programmable analog VLSI array processing. En 13th IEEE International Conference on Electronics, Circuits and Systems (1332-1335), Niza, Francia: Institute of Electrical and Electronics Engineers. | |
dc.identifier.isbn | 1-4244-0394-4 | es |
dc.identifier.uri | https://hdl.handle.net/11441/95253 | |
dc.description.abstract | This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs. | es |
dc.description.sponsorship | Office of Naval Research (USA) N-00014- 02-1-0884 | es |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología TIC2003-09817-C02-01 | es |
dc.format | application/pdf | es |
dc.format.extent | 4 p. | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | 13th IEEE International Conference on Electronics, Circuits and Systems (2006), p 1332-1335 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Robust symmetric multiplication for programmable analog VLSI array processing | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | N-00014- 02-1-0884 | es |
dc.relation.projectID | TIC2003-09817-C02-01 | es |
dc.relation.publisherversion | https://doi.org/10.1109/ICECS.2006.379728 | es |
dc.identifier.doi | 10.1109/ICECS.2006.379728 | es |
dc.publication.initialPage | 1332 | es |
dc.publication.endPage | 1335 | es |
dc.eventtitle | 13th IEEE International Conference on Electronics, Circuits and Systems | es |
dc.eventinstitution | Niza, Francia | es |