Artículo
Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+
Autor/es | Río Fernández, Rocío del
Rosa Utrera, José Manuel de la Pérez Verdú, Belén Delgado Restituto, Manuel Medeiro Hidalgo, Fernando Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2004 |
Fecha de depósito | 2018-09-06 |
Publicado en |
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Resumen | We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) ... We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator. |
Agencias financiadoras | European Union (UE) Ministerio de Ciencia y Tecnología (MCYT). España |
Identificador del proyecto | 29261/MIXMODEST
2001-34283/TAMES-2 TIC2001-0929/ADAVERE |
Cita | Río Fernández, R.d., Rosa Utrera, J.M.d.l., Pérez Verdú, B., Delgado Restituto, M., Medeiro Hidalgo, F. y Rodríguez Vázquez, Á.B. (2004). Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+. IEEE Transactions on Circuits and Systems I: Regular Papers, 51 (1), 47-62. |
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