dc.creator | Río Fernández, Rocío del | es |
dc.creator | Rosa Utrera, José Manuel de la | es |
dc.creator | Pérez Verdú, Belén | es |
dc.creator | Delgado Restituto, Manuel | es |
dc.creator | Medeiro Hidalgo, Fernando | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.date.accessioned | 2018-09-06T14:28:43Z | |
dc.date.available | 2018-09-06T14:28:43Z | |
dc.date.issued | 2004 | |
dc.identifier.citation | Río Fernández, R.d., Rosa Utrera, J.M.d.l., Pérez Verdú, B., Delgado Restituto, M., Medeiro Hidalgo, F. y Rodríguez Vázquez, Á.B. (2004). Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+. IEEE Transactions on Circuits and Systems I: Regular Papers, 51 (1), 47-62. | |
dc.identifier.issn | 1549-8328 | es |
dc.identifier.uri | https://hdl.handle.net/11441/78365 | |
dc.description.abstract | We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator. | es |
dc.description.sponsorship | European Union 29261/MIXMODEST, 2001-34283/TAMES-2 | es |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología TIC2001-0929/ADAVERE | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems I: Regular Papers, 51 (1), 47-62. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog-to-digital converters | es |
dc.subject | ADSL | es |
dc.subject | ΣΔ modulation | es |
dc.subject | Switched-capacitor circuits | es |
dc.title | Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+ | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | 29261/MIXMODEST | es |
dc.relation.projectID | 2001-34283/TAMES-2 | es |
dc.relation.projectID | TIC2001-0929/ADAVERE | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/TCSI.2003.821308 | es |
dc.identifier.doi | 10.1109/TCSI.2003.821308 | es |
idus.format.extent | 16 p. | es |
dc.journaltitle | IEEE Transactions on Circuits and Systems I: Regular Papers | es |
dc.publication.volumen | 51 | es |
dc.publication.issue | 1 | es |
dc.publication.initialPage | 47 | es |
dc.publication.endPage | 62 | es |
dc.contributor.funder | European Union (UE) | |
dc.contributor.funder | Ministerio de Ciencia y Tecnología (MCYT). España | |