Ponencia
Current-mode piecewise-linear function generators
Autor/es | Delgado Restituto, Manuel
Ceballos Cáceres, Joaquín Francisco Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1996 |
Fecha de depósito | 2019-10-28 |
Publicado en |
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ISBN/ISSN | 0-7803-3073-0 |
Resumen | We present a systematic design technique for current-mode piecewise-linear (PWL) function generators. It uses two building blocks: a high-resolution current rectifier, and a programmable current amplifier. We show how to ... We present a systematic design technique for current-mode piecewise-linear (PWL) function generators. It uses two building blocks: a high-resolution current rectifier, and a programmable current amplifier. We show how to arrange these blocks to obtain basic non-linearities from which generic characteristics are built through aggregations. Measurements from a 1.0 /spl mu/m CMOS prototype chip show 10 pA resolution in the rectification operation and 0.6% non-linearity errors in the programmable scaling operation for 2 /spl mu/A input current range. |
Cita | Delgado Restituto, M., Ceballos Cáceres, J.F. y Rodríguez Vázquez, Á.B. (1996). Current-mode piecewise-linear function generators. En IEEE International Symposium on Circuits and Systems (ISCAS) (469-472), Atlanta, USA: Institute of Electrical and Electronics Engineers. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Current-Mode Piecewise-Linear.pdf | 386.9Kb | [PDF] | Ver/ | |