Author profile: Juan Chico, Jorge
Institutional data
| Name | Juan Chico, Jorge |
| Department | Tecnología Electrónica |
| Knowledge area | Tecnología Electrónica |
| Professional category | Profesor Titular de Universidad |
| Request | |
 |
|
Statistics
-
No. publications
77
-
No. visits
7894
-
No. downloads
14616
| Publications |
|---|
Article
 IRIS: An embedded secure boot for IoT devices
(Elsevier, 2023-10-01)
This study proposes a hardware secure boot solution, an instant retrieval information system (IRIS) that is suitable for ... |
Article
An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation
(IEEE Computer Society, 2021-01-01)
This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the ... |
Article
Embedded LUKS (E-LUKS): A Hardware Solution to IoT Security
(MDPI, 2021-01-01)
The Internet of Things (IoT) security is one of the most important issues developers have to face. Data tampering must be ... |
Article
Address-encoded byte order
(Elsevier, 2020-01-01)
Unaligned accesses are forbidden in many high-performance architectures. In most of these architectures, the least significant ... |
Article
Using the complement of the cosine to compute trigonometric functions
(Springer, 2020-01-01)
The computation of the sine and cosine functions is required in devices ranging from application-specific signal processors ... |
Article
High-Performance Time Server Core for FPGA System-on-Chip
(MDPI, 2019-01-01)
This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core ... |
Presentation
La motivación en el aprendizaje de la Electrónica como mejora de la calidad de la educación
(Universidad de La Laguna, 2018-01-01)
La educación racional debe complementarse con la educación emocional (motivación), en esta, podemos destacar sus factores ... |
Article
Minimalistic SDHC-SPI hardware reader module for boot loader applications
(Elsevier, 2017-01-01)
This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The ... |
Presentation
eDSPlab+: Laboratorio remoto basado en Web Services
(Universidad de Sevilla, 2016-06-01)
En la actualidad existen multitud de propuestas de laboratorios de instrumentación electrónica que dan solución a una ... |
Presentation
Evolución de los MOOC en el ámbito investigador mediante técnicas de análisis de contenido
(Universidad de Sevilla, 2016-06-01)
Los Massive Open Online Courses (MOOCs) constituyen un nuevo modelo de docencia que ha ido ganando popularidad en los ... |
Presentation
Los proyectos de Ingeniería electrónica en el marco de los resultados de aprendizaje EUR-ACE
(Universidad de Sevilla, 2016-06-01)
El sello EUR-ACE® es un certificado que una agencia autorizada (en España ANECA) otorga a un título de grado o máster en ... |
Presentation
Acercamiento a una metodología científica en cursos de energía eólica para ingenieros electrónicos
(Universidad de Sevilla, 2016-06-01)
La docencia y la investigación son actividades que se realizan de manera simultánea en la práctica universitaria, pero ... |
Presentation
Análisis comparativo de distintas plataformas para la enseñanza de sistemas electrónicos digitales
(Universidad de Sevilla, 2016-06-01)
A la hora de enfocar la docencia de Sistemas Electrónicos Digitales, ha ido ganando sitio el uso de microcontroladores de ... |
Presentation
Procesamiento de bioseñales: un enfoque práctico
(Universidad de Sevilla, 2016-01-01)
La disciplina de procesamiento de bioseñales aparca un amplio y complejo espectro de conocimientos. El diseño de sesiones ... |
Presentation
Metodología PBL en modo colaborativo aplicada al diseño de un SoC
(Universidad de Sevilla, 2016-01-01)
Dado el carácter principalmente práctico en las asignaturas de los másteres universitarios la metodología PBL es ampliamente ... |
Presentation
Creación de carteles autoexplicativos para laboratorios de electrónica
(Universidad de Sevilla, 2016-01-01)
Se presenta un proyecto cuyo objetivo ha sido ha sido la creación de carteles que, a modo de tutoriales resumidos, muestran ... |
Presentation
Metodología de evaluación continua para grupos numerosos en Procesamiento de Señales Multimedia
(Universidad de Sevilla, 2016-01-01)
La asignatura de Procesamiento de Señales Multimedia utiliza una metodología de evaluación continua consistente en la ... |
Presentation
Aplicaciones docentes del diseño de un pico-procesador
(Universidad de Sevilla, 2016-01-01)
El conocimiento de la estructura interna y del mecanismo de funcionamiento de microprocesadores es una parte muy importante ... |
Presentation
evercodeML: a formal language for SoC integration
(IEEE Computer Society, 2015-01-01)
Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating ... |
Article
NanoFS: a hardware-oriented file system
(IEEE Computer Society, 2013-01-01)
NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to be ... |
Presentation
Experiencia de renovación metodológica en la enseñanza de la electrónica digital básica
(Universidad de Vigo, 2012-01-01)
Esta contribución presenta una experiencia sobre el proceso de adaptación de una asignatura de electrónica digital básica ... |
Presentation
Methodology Updating Experience in Basic Digital Electronics Teaching
(IEEE Computer Society, 2012-01-01)
This contribution describes the experience of updating a basic digital electronics course in a Computer Science grade as a ... |
Chapter of Book
Network Time Synchronization: A Full Hardware Approach
(Springer, 2012-01-01)
Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system ... |
| PhD Thesis |
Article
Long-term on-chip verification of systems with logical events scattered in time
(Elsevier, 2012-01-01)
Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the longterm verification ... |
PhD Thesis
Diseño e Implementación sobre FPGA de Sistemas Digitales de bajo coste para la Sincronización de Equipos sobre Redes de Comunicación usando el protocolo SNTP
(2011-01-01)
En este documento se presenta el trabajo de tesis doctoral realizado dentro del Programa de Doctorado "Informática Industrial" ... |
Article
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
(IEEE Computer Society, 2011-01-01)
Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most ... |
Presentation
Python as a hardware description language: A case study
(IEEE Computer Society, 2011-01-01)
Many people may see the development of software and hardware like different disciplines. However, there are great similarities ... |
Presentation
Design and implementation of a suitable core for on-chip long-term verification
(IEEE Computer Society, 2010-01-01)
Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the long-term verification ... |
Presentation
Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión
(Universidad de Alcalá, 2009-01-01)
Este trabajo presenta el diseño y la implementación sobre FPGA de un cliente SNTP compacto, de bajo coste y alta precisión, ... |
Presentation
Delay and power consumption of static bulk-CMOS gates using independent bodies
(IEEE Computer Society, 2009-01-01)
Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually ... |
Presentation
Efficient techniques and methodologies for embedded system design usign free hardware and open standards
(IEEE Computer Society, 2009-01-01)
|
Presentation
La primera experiencia en el diseño de sistemas digitales sobre FPGAs
(Universidad de Zaragoza, 2008-01-01)
Se presenta una práctica de introducción al diseño de sistemas digitales sobre FPGAs. El objetivo es que se pueda realizar ... |
Presentation
Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core
(IEEE Computer Society, 2008-01-01)
In this paper we present a design of a peripheral for MicroBlaze soft core processor as part of a R+D project carried out ... |
Presentation
La primera experiencia en el diseño de sistemas digitales sobre FPGAs
(Universidad Politécnica de Madrid, 2008-01-01)
Se presenta una práctica de introducción al diseño de sistemas digitales sobre FPGAs. El objetivo es que se pueda realizar ... |
| PhD Thesis |
Chapter of Book
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
(Springer, 2008-01-01)
Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static ... |
Presentation
Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution
(IEEE Computer Society, 2008-01-01)
This paper presents the design of a complete RTU (Remote Terminal Unit) with a System-on-Chip solution based completely ... |
Presentation
Design and Implementation of a SNTP Client on FPGA
(IEEE Computer Society, 2008-01-01)
This contribution presents the design and implementation of a SNTP client module suitable for IEC 61850 environments fully ... |
PhD Thesis
Simulación lógica temporal de altas prestaciones y aplicación a la estimación del consumo de potencia y corriente en circuitos integrados CMOS-VLSI
(2007-07-18)
El primer capítulo está dedicado a la simulación y verificación temporal de circuitos VLSI en general, así como a los ... |
Presentation
Design of a FFT/IFFT module as an IP core suitable for embedded systems
(IEEE Computer Society, 2007-01-01)
In this work, we have laid the foundations that allow us to accomplish the implementation of a FFT/IFFT module as an IP ... |
Chapter of Book
Static Power Consumption in CMOS Gates Using Independent Bodies
(Springer, 2007-01-01)
It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves ... |
Presentation
Automatic logic synthesis for parallel alternating latches clocking schemes
(SPIE Digital Library, 2007-01-01)
This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called ... |
Presentation
A SoC Design Methodology for LEON2 on FPGA
(IBERCHIP, 2006-01-01)
SoC design methodologies show up as a natural and productive method to implement embedded and/or ubiquitous systems. The ... |
Presentation
Diseño e Implementación Óptima de Periféricos de DSP con System Generator para Microblaze
(IBERCHIP, 2006-01-01)
Con este trabajo pretendemos analizar como se lleva a cabo el diseño de periféricos de DSP utilizando uno de los nuevos ... |
Presentation
Diseño e implantación de SoPC basados en el microprocesador PicoBlaze
(Universidad Politécnica de Madrid, 2006-01-01)
Con este trabajo pretendemos realizar una aportación a la docencia de la materias que cu bren el diseño de SoPC (System ... |
Presentation
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements
(IEEE Computer Society, 2006-01-01)
This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements ... |
Presentation
Diseño e implementación de SOPC basados en el microprocesador Picoblaze
(Universidad Politécnica de Madrid, 2006-01-01)
Con este trabajo pretendemos realizar una aportación a la docencia de la materias que cubren el diseño de SoPC (System on ... |
Presentation
Desarrollo en VHDL de un filtro digital genérico basado en estructuras canónicas.
(Universidad Politécnica de Madrid, 2006-01-01)
Este trabajo abarca la realización de un filtro digital a bajo nivel. El diseño propuesto se basa en la utilización de un ... |
Article
Automated performance evaluation of skew-tolerant clocking schemes
(Taylor and Francis Online, 2006-01-01)
In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes ... |
Presentation
Efficient Design of a FFT/IFFT-64 Module on ASIC
(IBERCHIP, 2005-01-01)
In this work we present the VHDL implementation of a FFT/IFFT-64 module. This implementation: (a) is relatively quick and ... |
Presentation
Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies
(IEEE Computer Society, 2005-01-01)
In the field of logic simulation, the constant advance of technology influences remarkably in the circuits dynamic behavior. ... |
Article
Application of Internode model to global power consumption estimation in SCMOS gates
(Springer, 2005-01-01)
In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based ... |
Presentation
Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
(Society of Photo-Optical Instrumentation Engineers (SPIE), 2005-01-01)
Nowadays it is not possible to neglect the delay of interconnection lines. The die size is rising very fast, and the delay ... |
Article
Power and timing modelling, optimisation and simulation
(Institute of Electrical and Electronics Engineers, 2005-01-01)
|
Chapter of Book
Logic-Level Fast Current Simulation for Digital CMOS Circuits
(Springer, 2005-01-01)
Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to ... |
Presentation
Análisis del comportamiento de la videoconsola Atari 2600 como sistema digital real basado en microprocesador en el laboratorio de electrónica.
(Universidad Politécnica de Valencia, 2004-01-01)
En este trabajo se propone una práctica de laboratorio para la asignatura Estructura de Computadores de primer curso de ... |
Presentation
ADKI: un sistema web de adquisición de datos bajo Linux
(Universidad Politécnica de Valencia, 2004-01-01)
Esta contribución presenta una aplicación genérica de adquisición de datos y control para sistemas simples que incorpora ... |
Article
Signal Sampling Based Transition Modeling for Digital Gates Characterization
(Springer, 2004-01-01)
Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel ... |
Presentation
Seguridad en Internet: web spoofing
(Universidad Politécnica de Valencia, 2004-01-01)
En este trabajo se estudia la técnica Web Spoofing como método de ataque a través de Internet. Se trata de una variante ... |
Presentation
Diseño del microcontrolador 8051 con módulo ensamblador- generador de ROM en lenguaje VHDL
(Universidad Politécnica de Valencia, 2004-01-01)
En este trabajo se presenta el resultado de un Proyecto Fin de Carrera en el que se ha diseñado el microcontrlador 8051 ... |
Presentation
Internode: Internal Node Logic Computational Model
(IEEE Computer Society, 2003-01-01)
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational ... |
Chapter of Book
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits
(Springer, 2003-01-01)
The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing ... |
Article
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)
(Springer, 2002-08-27)
In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which ... |
Chapter of Book
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
(Springer, 2002-01-01)
Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison ... |
Chapter of Book
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
(Springer, 2002-01-01)
This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current ... |
Presentation
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
(IEEE Computer Society, 2001-01-01)
As delay models used in logic timing simulation become more and more complex, the problem of model parameter values ... |
Presentation
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001-01-01)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation ... |
Presentation
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001-01-01)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the ... |
PhD Thesis
Degradación del retraso de propagación en puertas lógicas CMOS VLSI
(2000-10-20)
La evolución en la tecnología de circuitos VLSI da lugar, entre otras cosas, a un aumento en la escala de integración ... |
Presentation
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000-01-01)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the ... |
Chapter of Book
Degradation Delay Model Extension to CMOS Gates
(Springer, 2000-01-01)
This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic ... |
Presentation
Concepción de un microprocesador: de la especificación a la realización
(Universidad Politécnica de Madrid, 2000-01-01)
|
Chapter of Book
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
(Springer, 2000-01-01)
This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how ... |
Article
Aprendiendo a diseñar circuitos integrados digitales mediante el uso del ordenador
(Universidad de Sevilla, 1999-01-01)
En este trabajo se presenta una experiencia docente encaminada a mejorar la asimilación por parte de los alumnos de algunos ... |
Presentation
Delay degradation effect in submicronic CMOS inverters
(Université Catholique de Louvain, 1997-01-01)
This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS ... |
Article
Analysis of Metastable Operation in a CMOS Dynamic D-Latch
(Springer, 1997-01-01)
Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high ... |
