Ponencia
Delay and power consumption of static bulk-CMOS gates using independent bodies
Autor/es | Guerrero Martos, David
Millán Calderón, Alejandro Juan Chico, Jorge Bellido Díaz, Manuel Jesús Ruiz de Clavijo Vázquez, Paulino Ostúa Arangüena, Enrique |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2009 |
Fecha de depósito | 2021-02-09 |
Publicado en |
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ISBN/ISSN | 978-1-4244-4320-8 |
Resumen | Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages ... Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages obtained can justify its utilization in selected parts of the circuits. This is discussed in this paper. |
Agencias financiadoras | Ministerio de Educación y Ciencia (MEC). España |
Identificador del proyecto | TEC2007-61802/MIC (HIPER) |
Cita | Guerrero Martos, D., Millán Calderón, A., Juan Chico, J., Bellido Díaz, M.J., Ruiz de Clavijo Vázquez, P. y Ostúa Arangüena, E. (2009). Delay and power consumption of static bulk-CMOS gates using independent bodies. En DTIS 2009: 4th International Conference on Design amd Technology of Integrated Systems In Nanoscale Era (191-196), Cairo, Egypt: IEEE Computer Society. |
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