Ponencia
Delay degradation effect in submicronic CMOS inverters
Autor/es | Juan Chico, Jorge
Bellido Díaz, Manuel Jesús Acosta Jiménez, Antonio José Barriga Barros, Ángel Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1997 |
Fecha de depósito | 2021-02-18 |
Publicado en |
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Resumen | This communication presents the evidence of a degradation effect causing important
reductions in the delay of a CMOS inverter when consecutive input transition are close
in time. Complete understanding of the effect is ... This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library characterization as well as simulation at a transistor level. Comparison with HSPICE level 6 simulations shows satisfactory accuracy for timing evaluation. |
Agencias financiadoras | Comisión Interministerial de Ciencia y Tecnología (CICYT). España |
Identificador del proyecto | TIC 95-0094 |
Cita | Juan Chico, J., Bellido Díaz, M.J., Acosta Jiménez, A.J., Barriga Barros, Á. y Valencia Barrero, M. (1997). Delay degradation effect in submicronic CMOS inverters. En PATMOS 1997: 6th International Workshop on Power and Timing Modeling, Optimization and Simulation Louvain-la-Neuve, Belgium: Université Catholique de Louvain. |
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