dc.creator | Juan Chico, Jorge | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Acosta Jiménez, Antonio José | es |
dc.creator | Barriga Barros, Ángel | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.date.accessioned | 2021-02-18T09:26:47Z | |
dc.date.available | 2021-02-18T09:26:47Z | |
dc.date.issued | 1997 | |
dc.identifier.citation | Juan Chico, J., Bellido Díaz, M.J., Acosta Jiménez, A.J., Barriga Barros, Á. y Valencia Barrero, M. (1997). Delay degradation effect in submicronic CMOS inverters. En PATMOS 1997: 6th International Workshop on Power and Timing Modeling, Optimization and Simulation Louvain-la-Neuve, Belgium: Université Catholique de Louvain. | |
dc.identifier.uri | https://hdl.handle.net/11441/105110 | |
dc.description.abstract | This communication presents the evidence of a degradation effect causing important
reductions in the delay of a CMOS inverter when consecutive input transition are close
in time. Complete understanding of the effect is demonstrated, providing a quantifying
model. Fully characterization as a function of design variables and external conditions
is carried out, making the model suitable for using in library characterization as well as
simulation at a transistor level. Comparison with HSPICE level 6 simulations shows
satisfactory accuracy for timing evaluation. | es |
dc.description.sponsorship | Comisión Interministerial de Ciencia y Tecnología TIC 95-0094 | es |
dc.format | application/pdf | es |
dc.format.extent | 10 | es |
dc.language.iso | eng | es |
dc.publisher | Université Catholique de Louvain | es |
dc.relation.ispartof | PATMOS 1997: 6th International Workshop on Power and Timing Modeling, Optimization and Simulation (1997). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Delay degradation effect in submicronic CMOS inverters | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TIC 95-0094 | es |
dc.relation.publisherversion | http://xputers.informatik.uni-kl.de/conferences/patmos/patmos97/ | es |
dc.eventtitle | PATMOS 1997: 6th International Workshop on Power and Timing Modeling, Optimization and Simulation | es |
dc.eventinstitution | Louvain-la-Neuve, Belgium | es |
dc.relation.publicationplace | Louvain-la-Neuve, Belgium | es |
dc.contributor.funder | Comisión Interministerial de Ciencia y Tecnología (CICYT). España | es |