Data

NameAcosta Jiménez, Antonio José
DepartmentElectrónica y Electromagnetismo
Knowledge areaElectrónica
Professional categoryCatedrático de Universidad
E-mailRequest
           

  Statistics

  • Items

    39

  • Visits

    3173

  • Downloads

    4353

  Publications

 

Presentation
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Hamming-code based fault detection design methodology for block ciphers

Potestad Ordoñez, Francisco Eugenio; Tena Sánchez, Erica; Chaves, R.; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José; Jiménez Fernández, Carlos Jesús (IEEE Computer Society, 2020-01-01)
Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting ...
PhD Thesis
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Diseño y caracterización de criptocircuitos seguros y resistentes a ataques físicos.

Acosta Jiménez, Antonio José; Tena Sánchez, Erica (2019-03-11)
A diario personas de todo el mundo hacen uso de dispositivos electrónicos en los que almacenan o con los que intercambian ...
Final Degree Project
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Sistemas electrónicos para la asistencia, ayuda y recreación de personas con Discapacidad

Acosta Jiménez, Antonio José; Huertas Sánchez, Gloria; Jiménez Revuelta, José Carlos (2018-01-01)
Final Degree Project
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Diseño microelectrónico de circuitos criptográficos de altas prestaciones y evaluación de su seguridad

Acosta Jiménez, Antonio José; Tena Sánchez, Erica; Delgado Lozano, Ignacio María (2017-01-01)
Final Degree Project
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Procesado de señales eléctricas para la optimización de ataques laterales en circuitos criptográficos

Acosta Jiménez, Antonio José; Tena Sánchez, Erica; Domínguez Begines, José Manuel (2016-01-01)
Existen diversas formas de romper la seguridad de un sistema criptográfico. Una de ellas son los ataques de canal lateral ...
Presentation
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Low-power differential logic gates for dpa resistant circuits

Tena Sánchez, Erica; Castro, Javier; Acosta Jiménez, Antonio José (Institute of Electrical and Electronics Engineers, 2014-01-01)
Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks ...
Article
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A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions

Brox Jiménez, Piedad; Castro Ramírez, Javier; Martínez Rodríguez, Macarena Cristina; Tena Sánchez, Erica; Jiménez Fernández, Carlos Jesús; Baturone Castillo, María Iluminada; Acosta Jiménez, Antonio José (IEEE Computer Society, 2013-01-01)
This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated ...
Presentation
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ASIC-in-the-loop methodology for verification of piecewise affine controllers

Martínez Rodríguez, Macarena Cristina; Brox Jiménez, Piedad; Castro, Javier; Tena Sánchez, Erica; Acosta Jiménez, Antonio José; Baturone Castillo, María Iluminada (Institute of Electrical and Electronics Engineers, 2012-01-01)
This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable ...
Article
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An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors

Camuñas Mesa, Luis Alejandro; Zamarreño Ramos, Carlos; Linares Barranco, Alejandro; Acosta Jiménez, Antonio José; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2012-01-01)
Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) ...
Article
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A 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput

Camuñas Mesa, Luis Alejandro; Acosta Jiménez, Antonio José; Zamarreño Ramos, Carlos; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2011-01-01)
This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional ...
PhD Thesis
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Microchips convolucionadores AER para procesado asíncrono neocortical de información sensorial visual codificada en eventos

Acosta Jiménez, Antonio José; Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa; Camuñas Mesa, Luis Alejandro (2010-05-21)
En este trabajo, se presentan dos versiones diferentes de microchips convolucionadores completamente digitales basados en ...
Presentation
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Using physical unclonable functions for hardware authentication: a survey

Eiroa, Susana; Baturone Castillo, María Iluminada; Acosta Jiménez, Antonio José; Dávila, Jorge (2010-01-01)
Physical unclonable functions (PUFs) are drawing a crescent interest in hardware oriented security due to their special ...
Article
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CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking

Serrano Gotarredona, Rafael; Oster, Matthias; Lichtsteiner, Patrick; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Camuñas Mesa, Luis Alejandro; Berner, Raphael; Rivas Pérez, Manuel; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2009-01-01)
This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating ...
Presentation
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A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications

Villegas Calvo, José Alberto; Fiorelli Martegani, Rafaella Bianca; Ginés Arteaga, Antonio José; Doldan Lorenzo, Ricardo; Jalón, Maria Ángeles; Acosta Jiménez, Antonio José; Peralías Macías, Eduardo; Vázquez García de la Vega, Diego (2008-01-01)
This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and ...
Presentation
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La simulación eléctrica en el trabajo académicamente dirigido como vehículo docente para la enseñanza de la electrónica

Acosta Jiménez, Antonio José; Río Fernández, Rocío del; Rodríguez Vázquez, Ángel Benito (2008-01-01)
La Electrónica es una disciplina versátil en cuanto a las metodologías y técnicas docentes que pueden emplearse. Frente a ...
Article
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On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing

Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Serrano Gotarredona, Clara; Pérez Carrasco, José Antonio; Linares Barranco, Bernabé; Linares Barranco, Alejandro; Jiménez Moreno, Gabriel; Civit Balcells, Antón (IEEE Computer Society, 2008-01-01)
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The ...
Presentation
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Fully Digital AER Convolution Chip for Vision Processing

Camuñas Mesa, Luis Alejandro; Acosta Jiménez, Antonio José; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2008-01-01)
We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing ...
Presentation
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Asymmetric clock driver for improved power and noise performances

Castro, Javier; Parra Fernández, María del Pilar; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José (IEEE Computer Society, 2007-01-01)
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation ...
Article
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Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits

Acosta Jiménez, Antonio José; Mora Gutiérrez, José Miguel; Castro, Javier; Parra Fernández, María del Pilar (Society of Photo-optical Instrumentation Engineers, 2007-01-01)
The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and ...
Presentation
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Spike Events Processing for Vision Systems

Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Alejandro; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Linares Barranco, Bernabé (IEEE Computer Society, 2007-01-01)
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision ...
Article
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A neuromorphic cortical-layer microchip for spike-based event processing vision systems

Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2006-01-01)
We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing ...
Presentation
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High-speed image processing with AER-based components

Serrano Gotarredona, Rafael; Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Jiménez Moreno, Gabriel; Civit Balcells, Antón (IEEE Computer Society, 2006-01-01)
A high speed sample image processing application using AER-based components is presented. The setup objective is to ...
Presentation
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AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems

Serrano Gotarredona, Rafael; Oster, M.; Lichtsteiner, P.; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Kolle Riis, H.; Delbrück, Tobi; Liu, Shih-Chii; Zahnd, S.; Whatley, A.M.; Douglas, R.; Häfliger, P.; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Neural Information Processing Systems Foundation, 2005-01-01)
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the ...
Article
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A mixed-signal integrated circuit for FM-DCSK modulation

Delgado Restituto, Manuel; Acosta Jiménez, Antonio José; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2005-01-01)
This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential ...
Presentation
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Selective Clock-Gating for Low Power/Low Noise Synchronous Counters

Parra Fernández, María del Pilar; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (Springer, 2002-01-01)
The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to ...
Presentation
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Gate-Level Simulation of CMOS Circuits Using the IDDM Model

Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001-01-01)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the ...
Presentation
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HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model

Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001-01-01)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation ...
PhD Thesis
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Una aportación al diseño de circuitos integrados CMOS autotemporizados

Acosta Jiménez, Antonio José; Jiménez Naharro, Raúl (2000-07-10)
El auge que muestra el campo de los circuitos asíncronos en los últimos años es notorio. Por un lado cada vez se está ...
Chapter of Book
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Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits

Acosta Jiménez, Antonio José; Jiménez, R.; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel (Springer, 2000-01-01)
This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how ...
Chapter of Book
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Degradation Delay Model Extension to CMOS Gates

Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (Springer, 2000-01-01)
This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic ...
Presentation
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Inertial and Degradation Delay Model for CMOS Logic Gates

Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2000-01-01)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the ...
Presentation
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Delay degradation effect in submicronic CMOS inverters

Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Barriga Barros, Ángel; Valencia Barrero, Manuel (Université Catholique de Louvain, 1997-01-01)
This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS ...
Article
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Analysis of Metastable Operation in a CMOS Dynamic D-Latch

Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel; Huertas Díaz, José Luis (Springer, 1997-01-01)
Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high ...
Presentation
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New CMOS VLSI Linear Self-Timed Architectures

Acosta Jiménez, Antonio José; Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel; Barriga Barros, Ángel; Jiménez, R.; Huertas Díaz, José Luis (1995-01-01)
The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve ...
PhD Thesis
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Circuitos integrados CMOS autotemporizados

Barriga Barros, Ángel; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José (1994-01-01)
Presentation
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Modeling of Real Bistables in VHDL

Acosta Jiménez, Antonio José; Barriga Barros, Ángel; Valencia Barrero, Manuel; Bellido Díaz, Manuel Jesús; Huertas Díaz, José Luis (IEEE Computer Society, 1993-01-01)
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled ...
Presentation
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Un nuevo modelo de retraso para puertas lógicas CMOS

Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Núñez, R.; Barriga Barros, Ángel; Valencia Barrero, Manuel (Universidad de Málaga, 1993-01-01)
Los modelos de retraso para puertas lógicas, que usan la mayoría de los simuladores lógicos, carecen de la suficiente ...
Presentation
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Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores

Acosta Jiménez, Antonio José; Bellido Díaz, Manuel Jesús; Barriga Barros, Ángel; Valencia Barrero, Manuel (Universidad de Málaga, 1993-01-01)
La realización de sistemas digitales mediante técnicas autotemporizadas constituye la mejor alternativa para resolver la ...
Presentation
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Determinación del coeficiente de resolución en biestables RS CMOS

Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José; Barriga Barros, Ángel (Universidad Politécnica de Madrid. Laboratorio de Sistemas Integrados, 1992-01-01)
El diseño de biestables con riesgo de metaestabili­dad requiere que posean coeficientes de resolución adecuados. En este ...