Author profile: Acosta Jiménez, Antonio José
Institutional data
| Name | Acosta Jiménez, Antonio José |
| Department | Electrónica y Electromagnetismo |
| Knowledge area | Electrónica |
| Professional category | Catedrático de Universidad |
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Statistics
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No. publications
58
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No. visits
5554
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No. downloads
8828
| Publications |
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Article
 Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipherDesign and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
(IEEE, 2022-06-01)
Differential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the ... |
Article
Hardware Countermeasures Benchmarking Against Fault AttacksHardware Countermeasures Benchmarking Against Fault Attacks
(MDPI, 2022-02-01)
The development of differential fault analysis (DFA) techniques and mechanisms to inject faults into cryptographic circuits ... |
Article
Gate-Level Hardware Countermeasure Comparison against Power Analysis AttacksGate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
(MDPI, 2022-02-01)
The fast settlement of privacy and secure operations in the Internet of Things (IoT) is appealing in the selection of ... |
Chapter of Book
Design and security evaluation of secure cryptoharware (FPGA and ASIC) against hackers exploiting side-channel informationDesign and security evaluation of secure cryptoharware (FPGA and ASIC) against hackers exploiting side-channel information
(3ciencias, 2022-02-01)
Tradicionalmente, la seguridad en los dispositivos criptográficos estaba ligada exclusivamente a la fortaleza del algoritmo. ... |
Chapter of Book
Metodología de diseño para la detección de fallos en cifradores de bloques basada en códigos de HammingMetodología de diseño para la detección de fallos en cifradores de bloques basada en códigos de Hamming
(3ciencias, 2022-02-01)
La inserción de fallos y en concreto los análisis diferenciales de fallos (Differential Fault Analysis – DFA) se han ... |
Final Degree Project
Evaluation of PUF and QKD integration techniques as root of trust in communication systemsEvaluation of PUF and QKD integration techniques as root of trust in communication systems
(2022-01-01)
Quantum Cryptography could be the next key technology in terms of secure communication, but, as with every new technology, ... |
Final Degree Project
Desarrollo de setup experimental y control automático de instrumentos para optimizar ataques de canal lateralDesarrollo de setup experimental y control automático de instrumentos para optimizar ataques de canal lateral
(2022-01-01)
Un ataque de canal lateral explota un observable físico proveniente de un dispositivo criptográfico con el fin de extraer ... |
Presentation
Automated experimental setup for EM cartography to enhance EM attacksAutomated experimental setup for EM cartography to enhance EM attacks
(2022-01-01)
Side-channel attacks are a real threat, exploiting and revealing the secret data stored in our electronic devices ... |
Master's Final Project
Establecimiento y medida de figuras de seguridad criptográfica en función de la potenciaEstablecimiento y medida de figuras de seguridad criptográfica en función de la potencia
(2021-01-01)
Los ataques de canal lateral se utlizan para revelar datos secretos de dispositvos criptográfcos mediante la extracción ... |
Article
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETsGate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs
(IEEE, 2021-01-01)
The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an ... |
| Master's Final Project |
| Final Degree Project |
Presentation
Hamming-code based fault detection design methodology for block ciphersHamming-code based fault detection design methodology for block ciphers
(IEEE Computer Society, 2020-01-01)
Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting ... |
Article
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET TechnologiesProjection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies
(Association for Computing Machinery (ACM), 2020-01-01)
The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in ... |
PhD Thesis
Diseño y caracterización de criptocircuitos seguros y resistentes a ataques físicos.Diseño y caracterización de criptocircuitos seguros y resistentes a ataques físicos.
(2019-03-11)
A diario personas de todo el mundo hacen uso de dispositivos electrónicos en los que almacenan o con los que intercambian ... |
| Final Degree Project |
| Final Degree Project |
Article
Power and energy issues on lightweight cryptographyPower and energy issues on lightweight cryptography
(American Scientific Publishers, 2017-01-01)
Portable devices such as smartphones, smart cards and other embedded devices require encryption technology to guarantee ... |
Article
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overviewEmbedded electronic circuits for cryptography, hardware security and true random number generation: an overview
(Wiley-Blackwell, 2017-01-01)
We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic ... |
| Final Degree Project |
Final Degree Project
Procesado de señales eléctricas para la optimización de ataques laterales en circuitos criptográficosProcesado de señales eléctricas para la optimización de ataques laterales en circuitos criptográficos
(2016-01-01)
Existen diversas formas de romper la seguridad de un sistema criptográfico. Una de ellas son los ataques de canal lateral ... |
Presentation
Low-power differential logic gates for dpa resistant circuitsLow-power differential logic gates for dpa resistant circuits
(Institute of Electrical and Electronics Engineers, 2014-01-01)
Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks ... |
Article
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General PartitionsA Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions
(IEEE Computer Society, 2013-01-01)
This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated ... |
Presentation
ASIC-in-the-loop methodology for verification of piecewise affine controllersASIC-in-the-loop methodology for verification of piecewise affine controllers
(Institute of Electrical and Electronics Engineers, 2012-01-01)
This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable ... |
Article
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision SensorsAn Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors
(IEEE Computer Society, 2012-01-01)
Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) ... |
Article
A 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps ThroughputA 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
(IEEE Computer Society, 2011-01-01)
This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional ... |
PhD Thesis
Microchips convolucionadores AER para procesado asíncrono neocortical de información sensorial visual codificada en eventosMicrochips convolucionadores AER para procesado asíncrono neocortical de información sensorial visual codificada en eventos
(2010-05-21)
En este trabajo, se presentan dos versiones diferentes de microchips convolucionadores completamente digitales basados en ... |
Presentation
Using physical unclonable functions for hardware authentication: a surveyUsing physical unclonable functions for hardware authentication: a survey
(2010-01-01)
Physical unclonable functions (PUFs) are drawing a crescent interest in hardware oriented security due to their special ... |
Article
CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and trackingCAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking
(Institute of Electrical and Electronics Engineers, 2009-01-01)
This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating ... |
Presentation
Fully Digital AER Convolution Chip for Vision ProcessingFully Digital AER Convolution Chip for Vision Processing
(IEEE Computer Society, 2008-01-01)
We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing ... |
Presentation
La simulación eléctrica en el trabajo académicamente dirigido como vehículo docente para la enseñanza de la electrónicaLa simulación eléctrica en el trabajo académicamente dirigido como vehículo docente para la enseñanza de la electrónica
(2008-01-01)
La Electrónica es una disciplina versátil en cuanto a las metodologías y técnicas docentes que pueden emplearse. Frente a ... |
Article
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical ProcessingOn Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing
(IEEE Computer Society, 2008-01-01)
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The ... |
Presentation
A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communicationsA 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications
(2008-01-01)
This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and ... |
Presentation
Asymmetric clock driver for improved power and noise performancesAsymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007-01-01)
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation ... |
Presentation
Spike Events Processing for Vision SystemsSpike Events Processing for Vision Systems
(IEEE Computer Society, 2007-01-01)
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision ... |
Article
Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuitsEffects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits
(Society of Photo-optical Instrumentation Engineers, 2007-01-01)
The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and ... |
Presentation
High-speed image processing with AER-based componentsHigh-speed image processing with AER-based components
(IEEE Computer Society, 2006-01-01)
A high speed sample image processing application using AER-based components is presented. The setup objective is to ... |
Article
A neuromorphic cortical-layer microchip for spike-based event processing vision systemsA neuromorphic cortical-layer microchip for spike-based event processing vision systems
(Institute of Electrical and Electronics Engineers, 2006-01-01)
We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing ... |
Presentation
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision SystemsAER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
(Neural Information Processing Systems Foundation, 2005-01-01)
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the ... |
Article
A mixed-signal integrated circuit for FM-DCSK modulationA mixed-signal integrated circuit for FM-DCSK modulation
(Institute of Electrical and Electronics Engineers, 2005-01-01)
This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential ... |
Presentation
Selective Clock-Gating for Low Power/Low Noise Synchronous CountersSelective Clock-Gating for Low Power/Low Noise Synchronous Counters
(Springer, 2002-01-01)
The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to ... |
Presentation
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay modelHALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001-01-01)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation ... |
Presentation
Gate-Level Simulation of CMOS Circuits Using the IDDM ModelGate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001-01-01)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the ... |
PhD Thesis
Una aportación al diseño de circuitos integrados CMOS autotemporizadosUna aportación al diseño de circuitos integrados CMOS autotemporizados
(2000-07-10)
El auge que muestra el campo de los circuitos asíncronos en los últimos años es notorio. Por un lado cada vez se está ... |
Presentation
Inertial and Degradation Delay Model for CMOS Logic GatesInertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000-01-01)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the ... |
Chapter of Book
Degradation Delay Model Extension to CMOS GatesDegradation Delay Model Extension to CMOS Gates
(Springer, 2000-01-01)
This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic ... |
Presentation
Concepción de un microprocesador: de la especificación a la realizaciónConcepción de un microprocesador: de la especificación a la realización
(Universidad Politécnica de Madrid, 2000-01-01)
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Chapter of Book
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI CircuitsInfluence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
(Springer, 2000-01-01)
This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how ... |
Presentation
Un entorno informático de ayuda a la docencia de sistemas de comunicación optoelectrónicosUn entorno informático de ayuda a la docencia de sistemas de comunicación optoelectrónicos
(Universidad Politécnica de Madrid, 2000-01-01)
|
Presentation
Delay degradation effect in submicronic CMOS invertersDelay degradation effect in submicronic CMOS inverters
(Université Catholique de Louvain, 1997-01-01)
This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS ... |
Article
Analysis of Metastable Operation in a CMOS Dynamic D-LatchAnalysis of Metastable Operation in a CMOS Dynamic D-Latch
(Springer, 1997-01-01)
Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high ... |
Presentation
New CMOS VLSI Linear Self-Timed ArchitecturesNew CMOS VLSI Linear Self-Timed Architectures
(1995-01-01)
The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve ... |
Presentation
Aplicación del VHDL en prácticas de diseño de sistemas digitalesAplicación del VHDL en prácticas de diseño de sistemas digitales
(Universidad Politécnica de Madrid, 1994-01-01)
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| PhD Thesis |
Presentation
Un nuevo modelo de retraso para puertas lógicas CMOSUn nuevo modelo de retraso para puertas lógicas CMOS
(Universidad de Málaga, 1993-01-01)
Los modelos de retraso para puertas lógicas, que usan la mayoría de los simuladores lógicos, carecen de la suficiente ... |
Presentation
Modeling of Real Bistables in VHDLModeling of Real Bistables in VHDL
(IEEE Computer Society, 1993-01-01)
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled ... |
Presentation
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadoresArquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
(Universidad de Málaga, 1993-01-01)
La realización de sistemas digitales mediante técnicas autotemporizadas constituye la mejor alternativa para resolver la ... |
Presentation
Determinación del coeficiente de resolución en biestables RS CMOSDeterminación del coeficiente de resolución en biestables RS CMOS
(Universidad Politécnica de Madrid. Laboratorio de Sistemas Integrados, 1992-01-01)
El diseño de biestables con riesgo de metaestabilidad requiere que posean coeficientes de resolución adecuados. En este ... |