Author profile: Acosta Jiménez, Antonio José
Data
| Name | Acosta Jiménez, Antonio José |
| Department | Electrónica y Electromagnetismo |
| Knowledge area | Electrónica |
| Professional category | Catedrático de Universidad |
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Statistics
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Items
39
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Visits
3173
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Downloads
4353
| Publications |
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Presentation
 Hamming-code based fault detection design methodology for block ciphers
(IEEE Computer Society, 2020-01-01)
Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting ... |
PhD Thesis
Diseño y caracterización de criptocircuitos seguros y resistentes a ataques físicos.
(2019-03-11)
A diario personas de todo el mundo hacen uso de dispositivos electrónicos en los que almacenan o con los que intercambian ... |
| Final Degree Project |
| Final Degree Project |
Final Degree Project
Procesado de señales eléctricas para la optimización de ataques laterales en circuitos criptográficos
(2016-01-01)
Existen diversas formas de romper la seguridad de un sistema criptográfico. Una de ellas son los ataques de canal lateral ... |
Presentation
Low-power differential logic gates for dpa resistant circuits
(Institute of Electrical and Electronics Engineers, 2014-01-01)
Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks ... |
Article
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions
(IEEE Computer Society, 2013-01-01)
This paper presents a programmable and configurable architecture and its inclusion in an Application Specific Integrated ... |
Presentation
ASIC-in-the-loop methodology for verification of piecewise affine controllers
(Institute of Electrical and Electronics Engineers, 2012-01-01)
This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable ... |
Article
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors
(IEEE Computer Society, 2012-01-01)
Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) ... |
Article
A 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
(IEEE Computer Society, 2011-01-01)
This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional ... |
PhD Thesis
Microchips convolucionadores AER para procesado asíncrono neocortical de información sensorial visual codificada en eventos
(2010-05-21)
En este trabajo, se presentan dos versiones diferentes de microchips convolucionadores completamente digitales basados en ... |
Presentation
Using physical unclonable functions for hardware authentication: a survey
(2010-01-01)
Physical unclonable functions (PUFs) are drawing a crescent interest in hardware oriented security due to their special ... |
Article
CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking
(Institute of Electrical and Electronics Engineers, 2009-01-01)
This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating ... |
Presentation
A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications
(2008-01-01)
This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and ... |
Presentation
La simulación eléctrica en el trabajo académicamente dirigido como vehículo docente para la enseñanza de la electrónica
(2008-01-01)
La Electrónica es una disciplina versátil en cuanto a las metodologías y técnicas docentes que pueden emplearse. Frente a ... |
Article
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing
(IEEE Computer Society, 2008-01-01)
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The ... |
Presentation
Fully Digital AER Convolution Chip for Vision Processing
(IEEE Computer Society, 2008-01-01)
We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing ... |
Presentation
Asymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007-01-01)
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation ... |
Article
Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits
(Society of Photo-optical Instrumentation Engineers, 2007-01-01)
The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and ... |
Presentation
Spike Events Processing for Vision Systems
(IEEE Computer Society, 2007-01-01)
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision ... |
Article
A neuromorphic cortical-layer microchip for spike-based event processing vision systems
(Institute of Electrical and Electronics Engineers, 2006-01-01)
We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing ... |
Presentation
High-speed image processing with AER-based components
(IEEE Computer Society, 2006-01-01)
A high speed sample image processing application using AER-based components is presented. The setup objective is to ... |
Presentation
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
(Neural Information Processing Systems Foundation, 2005-01-01)
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the ... |
Article
A mixed-signal integrated circuit for FM-DCSK modulation
(Institute of Electrical and Electronics Engineers, 2005-01-01)
This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential ... |
Presentation
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
(Springer, 2002-01-01)
The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to ... |
Presentation
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001-01-01)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the ... |
Presentation
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001-01-01)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation ... |
PhD Thesis
Una aportación al diseño de circuitos integrados CMOS autotemporizados
(2000-07-10)
El auge que muestra el campo de los circuitos asíncronos en los últimos años es notorio. Por un lado cada vez se está ... |
Chapter of Book
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
(Springer, 2000-01-01)
This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how ... |
Chapter of Book
Degradation Delay Model Extension to CMOS Gates
(Springer, 2000-01-01)
This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic ... |
Presentation
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000-01-01)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the ... |
Presentation
Delay degradation effect in submicronic CMOS inverters
(Université Catholique de Louvain, 1997-01-01)
This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS ... |
Article
Analysis of Metastable Operation in a CMOS Dynamic D-Latch
(Springer, 1997-01-01)
Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high ... |
Presentation
New CMOS VLSI Linear Self-Timed Architectures
(1995-01-01)
The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve ... |
PhD Thesis
Circuitos integrados CMOS autotemporizados
(1994-01-01)
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Presentation
Modeling of Real Bistables in VHDL
(IEEE Computer Society, 1993-01-01)
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled ... |
Presentation
Un nuevo modelo de retraso para puertas lógicas CMOS
(Universidad de Málaga, 1993-01-01)
Los modelos de retraso para puertas lógicas, que usan la mayoría de los simuladores lógicos, carecen de la suficiente ... |
Presentation
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
(Universidad de Málaga, 1993-01-01)
La realización de sistemas digitales mediante técnicas autotemporizadas constituye la mejor alternativa para resolver la ... |
Presentation
Determinación del coeficiente de resolución en biestables RS CMOS
(Universidad Politécnica de Madrid. Laboratorio de Sistemas Integrados, 1992-01-01)
El diseño de biestables con riesgo de metaestabilidad requiere que posean coeficientes de resolución adecuados. En este ... |