Ponencia
Asymmetric clock driver for improved power and noise performances
Autor/es | Castro, Javier
Parra Fernández, María del Pilar ![]() ![]() ![]() ![]() ![]() ![]() Valencia Barrero, Manuel ![]() ![]() ![]() ![]() ![]() ![]() ![]() Acosta Jiménez, Antonio José ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2007 |
Fecha de depósito | 2017-10-03 |
Publicado en |
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ISBN/ISSN | 1-4244-0920-9 0271-4302 |
Resumen | One of the most important sources of switching
noise and power consumption in large VLSI circuits is the
clock generation and distribution tree. This paper analyzes
how the use of an asymmetric clock can be an ... One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an important solution to reduce the switching noise generated by the global clock, with a very reduced degradation in performances and reliability. The suited sizing of clock generators and the design of asymmetric clock tree cells, show the benefits of the proposed technique, validated through a design example where a 50% of noise reduction is achieved with 10% of loss in operation frequency and no penalty, even saving, in power consumption. |
Agencias financiadoras | Ministerio de Educación y Ciencia (MEC). España Junta de Andalucía |
Identificador del proyecto | TEC2004-01509
![]() TIC2006-635 ![]() |
Cita | Castro, J., Parra Fernández, M.d.P., Valencia Barrero, M. y Acosta, A.J. (2007). Asymmetric clock driver for improved power and noise performances. En ISCAS 2007 : IEEE International Symposium on Circuits and Systems (893-896), New Orleans, LA, USA: IEEE Computer Society. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Asymmetric clock driver.pdf | 321.2Kb | ![]() | Ver/ | |