Ponencia
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
Autor/es | Ruiz de Clavijo Vázquez, Paulino
Juan Chico, Jorge Bellido Díaz, Manuel Jesús Acosta Jiménez, Antonio José Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2001 |
Fecha de depósito | 2017-01-19 |
Publicado en |
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ISBN/ISSN | 0-7695-0993-2 1530-1591 |
Resumen | This communication presents HALOTIS, a novel high
accuracy logic timing simulation tool, that incorporates a
new simulation algorithm based on different concepts for
transitions and events. This new simulation algorithm ... This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators. |
Agencias financiadoras | Ministerio de Ciencia y Tecnología (MCYT). España |
Identificador del proyecto | TIC 2000-1350 |
Cita | Ruiz de Clavijo Vázquez, P., Juan Chico, J., Bellido Díaz, M.J., Acosta Jiménez, A.J. y Valencia Barrero, M. (2001). HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. En Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001 (467-471), Munich, Germany: IEEE Computer Society. |
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