Ponencia
Inertial and Degradation Delay Model for CMOS Logic Gates
Autor/es | Juan Chico, Jorge
Ruiz de Clavijo Vázquez, Paulino Bellido Díaz, Manuel Jesús Acosta Jiménez, Antonio José Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2000 |
Fecha de depósito | 2018-07-23 |
Publicado en |
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ISBN/ISSN | 0-7803-5482-6 |
Resumen | The authors present the Inertial and Degradation
Delay Model (IDDM) for CMOS digital simulation. The
model combines the Degradation Delay Model presented in
previous papers with a new algorithm to handle the inertial ... The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches. |
Cita | Juan Chico, J., Ruiz de Clavijo Vázquez, P., Bellido Díaz, M.J., Acosta Jiménez, A.J. y Valencia Barrero, M. (2000). Inertial and Degradation Delay Model for CMOS Logic Gates. En ISCAS 2000: IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century (I-459-I-462), Geneva, Switzerland: IEEE Computer Society. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Inertial and degradation.pdf | 360.7Kb | [PDF] | Ver/ | |