On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing
|Author||Serrano Gotarredona, Rafael
Serrano Gotarredona, María Teresa
Acosta Jiménez, Antonio José
Serrano Gotarredona, Clara
Pérez Carrasco, José Antonio
Linares Barranco, Bernabé
Linares Barranco, Alejandro
Jiménez Moreno, Gabriel
Civit Balcells, Antón
|Department||Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores
Universidad de Sevilla. Departamento de Teoría de la Señal y Comunicaciones
|Published in||IEEE Transactions on Neural Networks, 19 (7), 1196-1219.|
|Abstract||In this paper, a chip that performs real-time image
convolutions with programmable kernels of arbitrary shape is presented.
The chip is a first experimental prototype of reduced size
to validate the implemented circuits ...
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address–event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16x16 has been implemented with programmable kernel size of up to 16x16. The chip has been fabricated in a standard 0.35- m complimentary metal–oxide–semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog–digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.
|Cite||Serrano Gotarredona, R., Serrano Gotarredona, T., Acosta Jiménez, A.J., Serrano Gotarredona, C., Pérez Carrasco, J.A., Linares Barranco, B.,...,Civit Balcells, A. (2008). On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing. IEEE Transactions on Neural Networks, 19 (7), 1196-1219.|