dc.creator | Serrano Gotarredona, Rafael | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Acosta Jiménez, Antonio José | es |
dc.creator | Serrano Gotarredona, Clara | es |
dc.creator | Pérez Carrasco, José Antonio | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.creator | Jiménez Moreno, Gabriel | es |
dc.creator | Civit Balcells, Antón | es |
dc.date.accessioned | 2020-01-13T09:54:31Z | |
dc.date.available | 2020-01-13T09:54:31Z | |
dc.date.issued | 2008 | |
dc.identifier.citation | Serrano Gotarredona, R., Serrano Gotarredona, T., Acosta Jiménez, A.J., Serrano Gotarredona, C., Pérez Carrasco, J.A., Linares Barranco, B.,...,Civit Balcells, A. (2008). On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing. IEEE Transactions on Neural Networks, 19 (7), 1196-1219. | |
dc.identifier.issn | 1045-9227 | es |
dc.identifier.uri | https://hdl.handle.net/11441/91461 | |
dc.description.abstract | In this paper, a chip that performs real-time image
convolutions with programmable kernels of arbitrary shape is presented.
The chip is a first experimental prototype of reduced size
to validate the implemented circuits and system level techniques.
The convolution processing is based on the address–event-representation
(AER) technique, which is a spike-based biologically
inspired image and video representation technique that favors
communication bandwidth for pixels with more information. As
a first test prototype, a pixel array of 16x16 has been implemented
with programmable kernel size of up to 16x16. The
chip has been fabricated in a standard 0.35- m complimentary
metal–oxide–semiconductor (CMOS) process. The technique also
allows to process larger size images by assembling 2-D arrays of
such chips. Pixel operation exploits low-power mixed analog–digital
circuit techniques. Because of the low currents involved (down
to nanoamperes or even picoamperes), an important amount of
pixel area is devoted to mismatch calibration. The rest of the
chip uses digital circuit techniques, both synchronous and asynchronous.
The fabricated chip has been thoroughly tested, both at
the pixel level and at the system level. Specific computer interfaces
have been developed for generating AER streams from conventional
computers and feeding them as inputs to the convolution
chip, and for grabbing AER streams coming out of the convolution
chip and storing and analyzing them on computers. Extensive
experimental results are provided. At the end of this paper, we
provide discussions and results on scaling up the approach for
larger pixel arrays and multilayer cortical AER systems. | es |
dc.description.sponsorship | Commission of the European Communities IST-2001-34124 (CAVIAR) | es |
dc.description.sponsorship | Commission of the European Communities 216777 (NABAB) | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TIC-2000-0406-P4 | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TIC-2003-08164-C03-01 | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TEC2006-11730-C03-01 | es |
dc.description.sponsorship | Junta de Andalucía TIC-1417 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | IEEE Transactions on Neural Networks, 19 (7), 1196-1219. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Address event representation (AER) | es |
dc.subject | Analog circuits | es |
dc.subject | Asynchronous circuits | es |
dc.subject | Bioinspired systems | es |
dc.subject | Cortical layer processing | es |
dc.subject | Image convolutions | es |
dc.subject | Image processing | es |
dc.subject | Low power circuits | es |
dc.subject | Mixed-signal circuits | es |
dc.subject | Spike-based processing | es |
dc.title | On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Teoría de la Señal y Comunicaciones | es |
dc.relation.projectID | IST-2001-34124 (CAVIAR) | es |
dc.relation.projectID | 216777 (NABAB) | es |
dc.relation.projectID | TIC-2000-0406-P4 | es |
dc.relation.projectID | TIC-2003-08164-C03-01 | es |
dc.relation.projectID | TEC2006-11730-C03-01 | es |
dc.relation.projectID | TIC-1417 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/4490276 | es |
dc.identifier.doi | 10.1109/TNN.2008.2000163 | es |
idus.format.extent | 23 | es |
dc.journaltitle | IEEE Transactions on Neural Networks | es |
dc.publication.volumen | 19 | es |
dc.publication.issue | 7 | es |
dc.publication.initialPage | 1196 | es |
dc.publication.endPage | 1219 | es |
dc.identifier.sisius | 6628403 | es |