Capítulo de Libro
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
Autor/es | Ruiz de Clavijo Vázquez, Paulino
Juan Chico, Jorge Bellido Díaz, Manuel Jesús Millán Calderón, Alejandro Guerrero Martos, David |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2002 |
Fecha de depósito | 2017-01-19 |
Publicado en |
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ISBN/ISSN | 978-3-540-44143-4 0302-9743 |
Resumen | This contribution presents a method to obtain current estimations
at the logic level. This method uses a simple current model and
a current curve generation algorithm that is implemented as an attached
module to a logic ... This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach. |
Agencias financiadoras | Ministerio de Ciencia y Tecnología (MCYT). España |
Identificador del proyecto | TIC 2000-1350
TIC 2002-2283 |
Cita | Ruiz de Clavijo Vázquez, P., Juan Chico, J.,...,Guerrero Martos, D. (2002). Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. En Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451 (pp. 400-408). Berlin: Springer. |
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