Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

Author/s	Ruiz de Clavijo Vázquez, Paulino Juan Chico, Jorge Bellido Díaz, Manuel Jesús Millán Calderón, Alejandro Guerrero Martos, David
Department	Universidad de Sevilla. Departamento de Tecnología Electrónica
Date	2002
Published in	Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451
ISBN/ISSN	978-3-540-44143-4 0302-9743
Abstract	This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic ...
Funding agencies	Ministerio de Ciencia y Tecnología (MCYT). España
Project ID.	TIC 2000-1350 TIC 2002-2283
Citation	Ruiz de Clavijo Vázquez, P., Juan Chico, J.,...,Guerrero Martos, D. (2002). Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. En Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451 (pp. 400-408). Berlin: Springer.