Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Author/s	Millán Calderón, Alejandro Juan Chico, Jorge Bellido Díaz, Manuel Jesús Guerrero Martos, David Ruiz de Clavijo Vázquez, Paulino Viejo Cortés, Julián
Department	Universidad de Sevilla. Departamento de Tecnología Electrónica
Date	2008
Published in	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349
ISBN/ISSN	978-3-540-95947-2 0302-9743
Abstract	Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In ...
Funding agencies	Ministerio de Educación y Ciencia (MEC). España
Project ID.	HYPER MIC TEC2007-61802
Citation	Millán Calderón, A., Juan Chico, J.,...,Viejo Cortés, J. (2008). Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. En Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349 (pp. 389-398). Berlin: Springer.