Ponencia
evercodeML: a formal language for SoC integration
Autor/es | Villar de Ossorno, José Ignacio
Juan Chico, Jorge Guerrero Martos, David Bellido Díaz, Manuel Jesús Viejo Cortés, Julián |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2015 |
Fecha de depósito | 2021-02-12 |
Publicado en |
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ISBN/ISSN | 979-1-0922-7912-2 2117-4628 |
Resumen | Complex SoC design devote a great part of the
developing time to module integration tasks. The necessity of
automating system integration at high-level has yield to the
development of module description languages like ... Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like IP-XACT. However, the available options today still lack advanced parametrization capabilities needed to design complex systems with very heterogeneous IP-cores and module providers. This contribution introduces a formal language for SoC integration that overcomes these limitations. |
Agencias financiadoras | Ministerio de Ciencia e Innovación (MICIN). España |
Identificador del proyecto | TEC2011-27936 (HIPERSYS) |
Cita | Villar de Ossorno, J.I., Juan Chico, J., Guerrero Martos, D., Bellido Díaz, M.J. y Viejo Cortés, J. (2015). evercodeML: a formal language for SoC integration. En ESLsyn: 2015 Electronic System Level Synthesis Conference San Francisco, CA: IEEE Computer Society. |
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