Presentation
Internode: Internal Node Logic Computational Model
Author/s | Millán Calderón, Alejandro
![]() ![]() ![]() ![]() ![]() ![]() ![]() Bellido Díaz, Manuel Jesús ![]() ![]() ![]() ![]() ![]() ![]() Juan Chico, Jorge ![]() ![]() ![]() ![]() ![]() ![]() ![]() Guerrero Martos, David ![]() ![]() ![]() ![]() ![]() ![]() ![]() Ruiz de Clavijo Vázquez, Paulino ![]() ![]() ![]() ![]() ![]() ![]() Ostúa Arangüena, Enrique ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Department | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Date | 2003 |
ISBN/ISSN | 0-7695-1911-3 1080-241X |
Abstract | In this work, we present a computational behavioral
model for logic gates called Internode (Internal Node Logic
Computational Model) that considers the functionality of
the gate as well as all the different internal ... In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal states the gate can reach. This computational model can be used in logiclevel tools and is valid for any dynamic behavioral model (delay models, power models, switching noise models, etc.). Also, we show a very efficient implementation of the model, in C language, for -inputs SCMOS NOR/NAND gates. Finally, we demonstrate the functionality of the model showing three different examples of modeling: (a) a propagation delay model, (b) the degradation delay model (DDM), and (c) a simple power model |
Project ID. | TIC 2000-1350
![]() TIC 2002-2283 ![]() |
Citation | Millán Calderón, A., Bellido Díaz, M.J., Juan Chico, J., Guerrero Martos, D., Ruiz de Clavijo Vázquez, P. y Ostua Arangüena, E. (2003). Internode: Internal Node Logic Computational Model. En 36th Annual Simulation Symposium (ANSS-36 2003) (241-248), Orlando, Florida: IEEE Computer Society. |
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