Automated performance evaluation of skew-tolerant clocking schemes
|Guerrero Martos, David
Bellido Díaz, Manuel Jesús
Juan Chico, Jorge
Millán Calderón, Alejandro
Ruiz de Clavijo Vázquez, Paulino
Ostúa Arangüena, Enrique
Viejo Cortés, Julián
|Universidad de Sevilla. Departamento de Tecnología Electrónica
|In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: ...
In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase PALACS). In order to evaluate the timing performance, the authors introduce algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. From these waveforms it is possible to get parameters such as the non-overlapping time and the clock period. They have been implemented in a tool and have been used to compare the timing performance of the clocking schemes applied to a simple circuit. To analyse the power consumption the authors have electrically simulated a simple circuit for several operation frequencies. The most remarkable conclusion is that it is possible to save about 50% of the power consumption of the clock distribution network by using PALACS.
|Ministerio de Ciencia y Tecnología (MCYT). España
|Guerrero Martos, D., Bellido Díaz, M.J., Juan Chico, J., Millán Calderón, A., Ruiz de Clavijo Vázquez, P., Ostúa Arangüena, E. y Viejo Cortés, J. (2006). Automated performance evaluation of skew-tolerant clocking schemes. International Journal of Electronics, 93 (12), 819-842.