Capítulo de Libro
Logic-Level Fast Current Simulation for Digital CMOS Circuits
Autor/es | Ruiz de Clavijo Vázquez, Paulino
Juan Chico, Jorge Bellido Díaz, Manuel Jesús Millán Calderón, Alejandro Guerrero Martos, David Ostúa Arangüena, Enrique Viejo Cortés, Julián |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2005 |
Fecha de depósito | 2017-01-23 |
Publicado en |
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ISBN/ISSN | 978-3-540-29013-1 0302-9743 |
Resumen | Nowadays, verification of digital integrated circuit has been
focused more and more from the timing and area field to current and
power estimations. The main problem with this kind of verification is
on the lack of ... Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of precision of current estimations when working at higher levels (logic, RT, architectural levels). To solve this problem it is not only necessary to use good current models for switching activity but, also, it is necessary to calculate this switching activity with high accuracy. In this paper we present an alternative to estimate current consumption using logic-level simulation. To do that, we use a simple but accurate enough current model to calculate the current consumption for each signal transition, and a delay model that obtains high accuracy when it is used to measure the switching activity (the Degradation Delay Model -DDM-). In the paper we present the current model for CMOS inverter, the characterization process and the model implementation in the logic simulator HALOTIS that includes the DDM. Results show a high accuracy in the estimation of current curves when compared to HSPICE, and a potentially large improvement over conventional approaches. |
Agencias financiadoras | Ministerio de Educación y Ciencia (MEC). España |
Identificador del proyecto | TEC 2004-00840/MIC |
Cita | Ruiz de Clavijo Vázquez, P., Juan Chico, J.,...,Viejo Cortés, J. (2005). Logic-Level Fast Current Simulation for Digital CMOS Circuits. En Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. (pp. 425-435). Berlin: Springer. |
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