Ponencia
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
Autor/es | Juan Chico, Jorge
Bellido Díaz, Manuel Jesús Ruiz de Clavijo Vázquez, Paulino Baena Oliva, María del Carmen Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2001 |
Fecha de depósito | 2022-01-27 |
Publicado en |
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ISBN/ISSN | 0-7803-7057-0 |
Resumen | As delay models used in logic timing simulation
become more and more complex, the problem of model
parameter values extraction arise as an important issue,
which is necessary to face in order to achieve a practical
i ... As delay models used in logic timing simulation become more and more complex, the problem of model parameter values extraction arise as an important issue, which is necessary to face in order to achieve a practical implementation of the model. In this way, this communication describes the characterization process associated to the previously developed Delay Degradation Model for CMOS logic gates (DDM) and the implementation of an automatic characterization tool that automates the process and allows an easy and fast model parameters extraction. |
Cita | Juan Chico, J., Bellido Díaz, M.J., Ruiz de Clavijo Vázquez, P., Baena Oliva, M.d.C. y Valencia Barrero, M. (2001). AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model. En ICECS 2001: 8th IEEE International Conference on Electronics, Circuits and Systems (1631-1634), Malta: IEEE Computer Society. |
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