Presentation
Efficient Design of a FFT/IFFT-64 Module on ASIC
Author/s | Millán Calderón, Alejandro
![]() ![]() ![]() ![]() ![]() ![]() ![]() Bellido Díaz, Manuel Jesús ![]() ![]() ![]() ![]() ![]() ![]() Juan Chico, Jorge ![]() ![]() ![]() ![]() ![]() ![]() ![]() Ruiz de Clavijo Vázquez, Paulino ![]() ![]() ![]() ![]() ![]() ![]() Guerrero Martos, David ![]() ![]() ![]() ![]() ![]() ![]() ![]() Ostúa Arangüena, Enrique ![]() ![]() ![]() ![]() ![]() ![]() ![]() Viejo Cortés, Julián ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Department | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Publication Date | 2005 |
Deposit Date | 2021-02-10 |
Published in |
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ISBN/ISSN | 959-261-105-X |
Abstract | In this work we present the VHDL implementation of a
FFT/IFFT-64 module. This implementation: (a) is relatively
quick and (b) occupies a limited amount of area. The
module operation is based on a radix-8 butterfly and ... In this work we present the VHDL implementation of a FFT/IFFT-64 module. This implementation: (a) is relatively quick and (b) occupies a limited amount of area. The module operation is based on a radix-8 butterfly and it allows the calculation of a complex 64-element FFT/IFFT in 290 clock cycles providing a precision of 98.8% on the magnitude of the output samples. Area saving is achieved mainly by using a RAM macrocell in order to store intermediate calculations. The synthesis process has been carried out on ASIC using AMS 0.35 μm technology and reaching the place & routing level in the test process. |
Citation | Millán Calderón, A., Bellido Díaz, M.J., Juan Chico, J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D., Ostúa Arangüena, E. y Viejo Cortés, J. (2005). Efficient Design of a FFT/IFFT-64 Module on ASIC. En IWS 2005: XI Taller IBERCHIP Salvador de Bahía, Brasil: IBERCHIP. |
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