dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Guerrero Martos, David | es |
dc.creator | Ostúa Arangüena, Enrique | es |
dc.creator | Viejo Cortés, Julián | es |
dc.date.accessioned | 2021-02-10T09:16:50Z | |
dc.date.available | 2021-02-10T09:16:50Z | |
dc.date.issued | 2005 | |
dc.identifier.citation | Millán Calderón, A., Bellido Díaz, M.J., Juan Chico, J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D., Ostúa Arangüena, E. y Viejo Cortés, J. (2005). Efficient Design of a FFT/IFFT-64 Module on ASIC. En IWS 2005: XI Taller IBERCHIP Salvador de Bahía, Brasil: IBERCHIP. | |
dc.identifier.isbn | 959-261-105-X | es |
dc.identifier.uri | https://hdl.handle.net/11441/104801 | |
dc.description.abstract | In this work we present the VHDL implementation of a
FFT/IFFT-64 module. This implementation: (a) is relatively
quick and (b) occupies a limited amount of area. The
module operation is based on a radix-8 butterfly and it allows
the calculation of a complex 64-element FFT/IFFT
in 290 clock cycles providing a precision of 98.8% on the
magnitude of the output samples. Area saving is achieved
mainly by using a RAM macrocell in order to store intermediate
calculations. The synthesis process has been carried
out on ASIC using AMS 0.35 μm technology and reaching
the place & routing level in the test process. | es |
dc.format | application/pdf | es |
dc.format.extent | 6 | es |
dc.language.iso | eng | es |
dc.publisher | IBERCHIP | es |
dc.relation.ispartof | IWS 2005: XI Taller IBERCHIP (2005). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Efficient Design of a FFT/IFFT-64 Module on ASIC | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.publisherversion | http://161.111.232.132/iberchip2005/sesions/c3.htm | es |
dc.contributor.group | Universidad de Sevilla. TIC204: Investigación y Desarrollo Digital | es |
dc.eventtitle | IWS 2005: XI Taller IBERCHIP | es |
dc.eventinstitution | Salvador de Bahía, Brasil | es |
dc.relation.publicationplace | Salvador de Bahía, Brasil | es |