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Application of Internode model to global power consumption estimation in SCMOS gates

 

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Opened Access Application of Internode model to global power consumption estimation in SCMOS gates
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Author: Millán Calderón, Alejandro
Bellido Díaz, Manuel Jesús
Juan Chico, Jorge
Ruiz de Clavijo Vázquez, Paulino
Guerrero Martos, David
Ostúa Aranguena, Enrique
Viejo Cortés, Julián
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Date: 2005
Published in: Lecture Notes in Computer Science, 3728, 337-347.
Document type: Article
Abstract: In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal power consumption (such effect occurs when an input transition does not affect the output) in three different technologies (AMS 0.6 um, AMS 0.35 um, and UMC 130 nm). This consumption becomes more remarkable as technology advances yielding to underestimating up to 9.4% of global power consumption in the UMC 130 nm case. Finally, we show how to optimize power estimation in the SCMOS NOR-2 gate by applying Internode to modeling its consumption accurately.
Cite: Millán Calderón, A., Bellido Díaz, M.J., Juan Chico, J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D., Ostúa Arangüena, E. y Viejo Cortés, J. (2005). Application of Internode model to global power consumption estimation in SCMOS gates. Lecture Notes in Computer Science, 3728, 337-347.
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URI: http://hdl.handle.net/11441/49770

DOI: 10.1007/11556930

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