dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Guerrero Martos, David | es |
dc.creator | Ostúa Arangüena, Enrique | es |
dc.creator | Viejo Cortés, Julián | es |
dc.date.accessioned | 2016-12-07T08:56:07Z | |
dc.date.available | 2016-12-07T08:56:07Z | |
dc.date.issued | 2005 | |
dc.identifier.citation | Millán Calderón, A., Bellido Díaz, M.J., Juan Chico, J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D., Ostúa Arangüena, E. y Viejo Cortés, J. (2005). Application of Internode model to global power consumption estimation in SCMOS gates. Lecture Notes in Computer Science, 3728, 337-347. | |
dc.identifier.issn | 0302-9743 | es |
dc.identifier.uri | http://hdl.handle.net/11441/49770 | |
dc.description.abstract | In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal power consumption (such effect occurs when an input transition does not affect the output) in three different technologies (AMS 0.6 um, AMS 0.35 um, and UMC 130 nm). This consumption becomes more remarkable as technology advances yielding to underestimating up to 9.4% of global power consumption in the UMC 130 nm case. Finally, we show how to optimize power estimation in the SCMOS NOR-2 gate by applying Internode to modeling its consumption accurately. | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TEC 2004-00840/MIC | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Springer | es |
dc.relation.ispartof | Lecture Notes in Computer Science, 3728, 337-347. | es |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Application of Internode model to global power consumption estimation in SCMOS gates | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | META project TEC 2004-00840/MIC | es |
dc.relation.publisherversion | http://link.springer.com/chapter/10.1007/11556930_35 | es |
dc.identifier.doi | 10.1007/11556930 | es |
dc.contributor.group | Universidad de Sevilla. TIC-180: Diseño de Circuitos Integrados Digitales y Mixtos | es |
idus.format.extent | 11 | es |
idus.validador.nota | Según Sherpa Romeo: La versión de editor/PDF no puede utilizarse. El autor puede archivar la versión pre-print (ie la versión previa a la revisión por pares) o la versión post-print (ie la versión final posterior a la revisión por pares) | es |
dc.journaltitle | Lecture Notes in Computer Science | es |
dc.publication.volumen | 3728 | es |
dc.publication.initialPage | 337 | es |
dc.publication.endPage | 347 | es |
dc.identifier.idus | https://idus.us.es/xmlui/handle/11441/49770 | |
dc.contributor.funder | Ministerio de Educación y Ciencia (MEC). España | |