Ponencia
An error-controlled methodology for approximate hierarchical symbolic analysis
Autor/es | Guerra Vinuesa, Oscar
Rodríguez García, Juan D. Roca Moreno, Elisenda Fernández Fernández, Francisco Vidal Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2000 |
Fecha de depósito | 2020-04-17 |
Publicado en |
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ISBN/ISSN | 0-7803-5482-6 |
Resumen | Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical ... Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results. |
Identificador del proyecto | ESPRIT 21812
TIC97-0580 |
Cita | Guerra Vinuesa, O., Rodríguez García, J.D., Roca Moreno, E., Fernández Fernández, F.V. y Rodríguez Vázquez, Á.B. (2000). An error-controlled methodology for approximate hierarchical symbolic analysis. En IEEE International Symposium on Circuits and Systems (ISCAS) (III-133-III-136), Ginebra, Suiza: Institute of Electrical and Electronics Engineers. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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An Error-Controlled Methodology.pdf | 416.1Kb | [PDF] | Ver/ | |