Perfil del autor: Fernández Fernández, Francisco Vidal
Datos institucionales
| Nombre | Fernández Fernández, Francisco Vidal |
| Departamento | Electrónica y Electromagnetismo |
| Área de conocimiento | Electrónica |
| Categoría profesional | Catedrático de Universidad |
| Correo electrónico | Solicitar |
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Estadísticas
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Nº publicaciones
62
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Nº visitas
5197
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Nº descargas
5691
| Publicaciones |
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Artículo
 PACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs
(Institute of Electrical and Electronics Engineers, 2023)
In this paper, the application of regression-based supervised machine learning (ML) methods to the modeling of integrated ... |
Tesis Doctoral
Study of variability phenomena on CMOS technologies for its mitigation and exploitation
(2021)
Variability phenomena in CMOS technologies have become a growing concern in recent years. One of the main reasons for this ... |
| Tesis Doctoral |
Artículo
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs
(Institute of Electrical and Electronics Engineers, 2021)
This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses ... |
Artículo
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level
(Elsevier B.V., 2020)
In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, ... |
Artículo
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators ... |
Artículo
Flexible Setup for the Measurement of CMOS Time-Dependent Variability with Array-Based Integrated Circuits
(IEEE, 2020)
This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS ... |
Artículo
Chaotic image encryption using hopfield and hindmarsh–rose neurons implemented on FPGA
(Multidisciplinary Digital Publishing Institute (MDPI), 2020)
Chaotic systems implemented by artificial neural networks are good candidates for data encryption. In this manner, this ... |
Artículo
A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors
(Elsevier, 2019)
Random Telegraph Noise (RTN)has attracted increasing interest in the last years. This phenomenon introduces variability ... |
Artículo
 A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate ... |
Artículo
PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors
(MDPI, 2019)
Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for ... |
Tesis Doctoral
Una aproximación multinivel para el diseño sistemático de circuitos integrados de radiofrecuencia.
(2018)
En un mercado bien establecido como el de las telecomunicaciones, donde se está evolucionando hacia el 5G, se estima que ... |
Tesis Doctoral
Diseño de circuitos analógicos y de señal mixta con consideraciones de diseño físico y variabilidad
(2017)
Advances in microelectronic technology has been based on an increasing capacity to integrate transistors, moving this ... |
Artículo
Parametric macromodeling of integrated inductors for RF circuit design
(Wiley-Blackwell, 2017)
Nowadays, parametric macromodeling techniques are widely used to describe electromagnetic structures. In this contribution, ... |
Artículo
An automated design methodology of RF circuits by using Pareto-optimal fronts of EMsimulated inductors
(Institute of Electrical and Electronics Engineers, 2017)
A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the ... |
Artículo
Introduction to the special issue on SMACD 2012
(Springer, 2014)
Welcome to the Special Issue devoted to the 2012 edition of the International Conference on Synthesis, Modeling, Analysis ... |
Artículo
Context-dependent transformation of Pareto-optimal performance fronts of operational amplifiers
(Springer, 2012)
The use of Pareto-optimal performance fronts in emerging design methodologies for analog integrated circuits is a keystone ... |
Artículo
Pathological element-based active device models and their application to symbolic analysis
(Institute of Electrical and Electronics Engineers, 2011)
This paper proposes new pathological element-based active device models which can be used in analysis tasks of linear(ized) ... |
Artículo
Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques
(Institute of Electrical and Electronics Engineers, 2011)
In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and response-surface-based ... |
Ponencia
Load-independent characterization of trade-off fronts for operational amplifiers
(2010)
Abstract—In emerging design methodologies for analog integrated circuits, the use of performance trade-off fronts, also ... |
Artículo
AMS/RF-CMOS circuit design for wireless transceivers
(Elsevier, 2009)
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Artículo
Editorial (Integration, the VLSI Journal)
(Elsevier, 2008)
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| Artículo |
Ponencia
A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator
(Institute of Electrical and Electronics Engineers, 2007)
This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, ... |
Artículo
A design tool for high-resolution high-frequency cascade continuous- time Σ∆ modulators
(SPIE, 2007)
This paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade ... |
Ponencia
Design of a 1.2-V Cascade Continuous-Time Sigma-Delta Modulator for Broadband Telecommunications
(Institute of Electrical and Electronics Engineers, 2006)
This paper presents the design of a continuous-time multibit cascade 2-2-1 sigma-delta modulator for broadband telecom systems. |
Ponencia
Reconfiguration of Cascade ΣΔ Modulators for Multistandard GSM/Bluetooth/UIMTS/WLAN Transceivers
(Institute of Electrical and Electronics Engineers, 2006)
This paper presents design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multi-standard wireless ... |
Ponencia
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator
(Institute of Electrical and Electronics Engineers, 2006)
This paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. ... |
Artículo
A new high-level synthesis methodology of cascaded continuous-time ΣΔ modulators
(Institute of Electrical and Electronics Engineers, 2006)
This brief presents an efficient method for synthesizing cascaded sigma–delta modulators implemented with continuous-time ... |
Ponencia
A Reuse-based framework for the design of analog and mixed-signal ICs
(The International Society for Optical Engineering -SPIE, 2005)
Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under ... |
Ponencia
Geometrically-constrained, parasitic-aware synthesis of analog ICs
(The International Society for Optical Engineering - SPIE, 2005)
In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as ... |
Artículo
High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a high-level synthesis tool for ΣΔ Modulators (ΣΔMs) that combines an accurate SIMULINK-based time-domain ... |
Ponencia
Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study
(The International Society for Optical Engineering - SPIE, 2005)
This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber ... |
Ponencia
Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC
(2005)
This paper analyses the effect of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero ... |
Ponencia
On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis
(The International Society for Optical Engineering - SPIE, 2005)
Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between ... |
Ponencia
A Direct Synthesis Method of Cascaded Continuous-Time Sigma-Delta Modulators
(2005)
This paper presents an efficient method to synthesize cascaded sigma-delta modulators implemented with continuous-time ... |
Ponencia
Analysis of Clock Jitter Error in Multibit Continuous-Time ΣΔ modulators with NRZ Feedback Waveform
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a detailed study of the clock jitter error in multibit continuous-time ΣΔ modulators with non-return-to-zero ... |
Ponencia
MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time Sigma-Delta Modulators
(Institute of Electrical and Electronics Engineers, 2004)
This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical ... |
Ponencia
An Optimization-based Tool for the High-Level Synthesis of Discrete-time and continuous-Time Sigma-Delta Modulators in the MATLAB/SIMULINK Environment
(Institute of Electrical and Electronics Engineers, 2004)
This paper presents a MATLAB toolbox for the automated high-level sizing of ΣΔ Modulators (ΣΔMs) based on the combination ... |
Ponencia
Accurate VHDL-based simulation of Sigma Delta modulators
(Institute of Electrical and Electronics Engineers, 2003)
The computational cost of transient simulation of /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) at the ... |
Artículo
Analog and mixed-signal IC design and design methodologies
(Elsevier, 2003)
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Ponencia
Generation of technology-portable flexible analog blocks
(Institute of Electrical and Electronics Engineers, 2002)
This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even ... |
Ponencia
An error-controlled methodology for approximate hierarchical symbolic analysis
(Institute of Electrical and Electronics Engineers, 2000)
Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, ... |
Ponencia
A hierarchical approach for the symbolic analysis of large analog integrated circuits
(IEEE computer society digital library, 2000)
This paper introduces a new hierarchical analysis methodology which incorporates approximation strategies during the ... |
Ponencia
An accurate error control mechanism for simplification before generation algorithms
(Institute of Electrical and Electronics Engineers, 1999)
The use of simplification before generation techniques to enable the approximate symbolic analysis of large analog circuits ... |
Ponencia
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design
(Institute of Electrical and Electronics Engineers, 1999)
This paper describes ESPRIT 29648, concerning the development of an advanced methodology for the design of a mixed-signal ... |
Artículo
Error control in simplification before generation algorithms for symbolic analysis of large analogue circuits
(Institution of Engineering and Technology, 1999)
Circuit reduction is a fundamental first step in addressing the symbolic analysis of large analogue circuits. A new algorithm ... |
Capítulo de Libro
Symbolic analysis of large analog integrated circuits: the numerical reference generation problem
(IEEE press, 1998)
Symbolic analysis potentialities for gaining circuit insight and for efficient repetitive evaluations have been limited ... |
Ponencia
Behavioral modeling of PWL analog circuits using symbolic analysis
(Institute of Electrical and Electronics Engineers, 1998)
Behavioral models are used both for top-down design and for bottom-up verification. During top-down design, models are ... |
Ponencia
An algorithm for numerical reference generation in symbolic analysis of large analog circuits
(Institute of Electrical and Electronics Engineers, 1997)
This paper addresses the problems arising in the calculation of numerical references (network function coefficients), ... |
Ponencia
Mismatch distance term compensation in centroid configurations with nonzero-area devices
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents an analytical approach to distance term compensation in mismatch models of integrated devices. Firstly, ... |
Ponencia
Comparison of matroid intersection algorithms for large circuit analysis
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents two approaches to symbolic analysis of large analog integrated circuits via simplification during the ... |
Ponencia
Symbolic analysis tools-the state of the art
(Institute of Electrical and Electronics Engineers, 1996)
This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state of the art in this field is also studied, pointing out directions for future research. |
Ponencia
A Family of matroid intersection algorithms for the computation of approximated symbolic network functions
(Institute of Electrical and Electronics Engineers, 1996)
In recent years, the technique of simplification during generation has turned out to be very promising for the efficient ... |
Artículo
Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits
(Institute of Electrical and Electronics Engineers, 1995)
A symbolic analysis tool is presented that generates simplified symbolic expressions for the small-signal characteristics ... |
Ponencia
Tool for fast mismatch analysis of analog circuits
(Institute of Electrical and Electronics Engineers, 1995)
A tool is presented that evaluates statistical deviations in performance characteristics of analog circuits, starting from ... |
Artículo
Global design of analog cells using statistical optimization techniques
(Springer, 1994)
We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. ... |
Ponencia
Symbolic analysis of large analog integrated circuits by approximation during expression generation
(Institute of Electrical and Electronics Engineers, 1994)
A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large ... |
Artículo
Algorithm for efficient symbolic analysis of large analogue circuits
(Institution of Engineering and Technology, 1994)
An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large ... |
Ponencia
On simplification techniques for symbolic analysis of analog integrated circuits
(Institute of Electrical and Electronics Engineers, 1992)
This paper addresses the topic of formula simplification for symbolic analyzers. Previously reported criteria for flat ... |
| Tesis Doctoral |
Ponencia
An advanced symbolic analyzer for the automatic generation of analog circuit design equations
(Institute of Electrical and Electronics Engineers, 1991)
A tool for symbolic analysis of analog integrated circuits is presented featuring accurate simplification, pole/zero ... |