An error-controlled methodology for approximate hierarchical symbolic analysis

Guerra Vinuesa, Oscar; Rodríguez García, Juan D.; Roca Moreno, Elisenda; Fernández Fernández, Francisco Vidal; Rodríguez Vázquez, Ángel Benito

doi:10.1109/ISCAS.2000.856014

Ponencia

dc.creator	Guerra Vinuesa, Oscar	es
dc.creator	Rodríguez García, Juan D.	es
dc.creator	Roca Moreno, Elisenda	es
dc.creator	Fernández Fernández, Francisco Vidal	es
dc.creator	Rodríguez Vázquez, Ángel Benito	es
dc.date.accessioned	2020-04-17T14:06:06Z
dc.date.available	2020-04-17T14:06:06Z
dc.date.issued	2000
dc.identifier.citation	Guerra Vinuesa, O., Rodríguez García, J.D., Roca Moreno, E., Fernández Fernández, F.V. y Rodríguez Vázquez, Á.B. (2000). An error-controlled methodology for approximate hierarchical symbolic analysis. En IEEE International Symposium on Circuits and Systems (ISCAS) (III-133-III-136), Ginebra, Suiza: Institute of Electrical and Electronics Engineers.
dc.identifier.isbn	0-7803-5482-6	es
dc.identifier.uri	https://hdl.handle.net/11441/95385
dc.description.abstract	Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results.	es
dc.description.sponsorship	European Commission ESPRIT 21812	es
dc.description.sponsorship	Comisión Interministerial de Ciencia y Tecnología TIC97-0580	es
dc.format	application/pdf	es
dc.format.extent	4 p.	es
dc.language.iso	eng	es
dc.publisher	Institute of Electrical and Electronics Engineers	es
dc.relation.ispartof	IEEE International Symposium on Circuits and Systems (ISCAS) (2000), pp. III-133-III-136.
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.title	An error-controlled methodology for approximate hierarchical symbolic analysis	es
dc.type	info:eu-repo/semantics/conferenceObject	es
dcterms.identifier	https://ror.org/03yxnpp24
dc.type.version	info:eu-repo/semantics/acceptedVersion	es
dc.rights.accessRights	info:eu-repo/semantics/openAccess	es
dc.contributor.affiliation	Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo	es
dc.relation.projectID	ESPRIT 21812	es
dc.relation.projectID	TIC97-0580	es
dc.relation.publisherversion	https://doi.org/10.1109/ISCAS.2000.856014	es
dc.identifier.doi	10.1109/ISCAS.2000.856014	es
dc.publication.initialPage	III-133	es
dc.publication.endPage	III-136	es
dc.eventtitle	IEEE International Symposium on Circuits and Systems (ISCAS)	es
dc.eventinstitution	Ginebra, Suiza	es
dc.identifier.sisius	5402116	es

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