FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration

Author	Senhadji Navarro, Raouf García Vargas, Ignacio Jiménez Moreno, Gabriel Civit Balcells, Antón
Department	Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores
Date	2007
Published in	ICECS 2007: 14th IEEE International Conference on Electronics, Circuits and Systems (2007), p 178-181
ISBN/ISSN	978-1-4244-1377-5
Abstract	In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in ...
Project ID.	TEC2006-11730-C03-02
Citation	Senhadji Navarro, R., García Vargas, I., Jiménez Moreno, G. y Civit Balcells, A. (2007). FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration. En ICECS 2007: 14th IEEE International Conference on Electronics, Circuits and Systems (178-181), Marrakech, Morocco: IEEE Computer Society.