Ponencia
FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration
Autor/es | Senhadji Navarro, Raouf
García Vargas, Ignacio Jiménez Moreno, Gabriel Civit Balcells, Antón |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2007 |
Fecha de depósito | 2019-12-10 |
Publicado en |
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ISBN/ISSN | 978-1-4244-1377-5 |
Resumen | In this paper, we present a HDL description of a
RAM with asymmetric port widths which allows read and
write operations with different data size. This RAM is suitable
for implementing run-time reconfigurable systems in ... In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA. The proposed RAM specification has been tested with different target devices. |
Identificador del proyecto | TEC2006-11730-C03-02 |
Cita | Senhadji Navarro, R., García Vargas, I., Jiménez Moreno, G. y Civit Balcells, A. (2007). FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration. En ICECS 2007: 14th IEEE International Conference on Electronics, Circuits and Systems (178-181), Marrakech, Morocco: IEEE Computer Society. |
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