Perfil del autor: García Vargas, Ignacio
Datos institucionales
| Nombre | García Vargas, Ignacio |
| Departamento | Arquitectura y Tecnología de Computadores |
| Área de conocimiento | Arquitectura y Tecnología de Computadores |
| Categoría profesional | Profesor Contratado Doctor |
| Correo electrónico | Solicitar |
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Estadísticas
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Nº publicaciones
21
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Nº visitas
2120
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Nº descargas
6822
| Publicaciones |
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Artículo
 A New Approach for Implementing Finite State Machines with Input Multiplexing
(MDPI, 2023)
The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite ... |
Artículo
Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations
(MDPI, 2023)
This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). ... |
Artículo
Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing
(Springer, 2022)
Finite State Machines with Input Multiplexing (FSMIMs) were proposed in previous work as a technique for efficient mapping ... |
Artículo
Mapping arbitrary logic functions onto carry chains in FPGAs
(MDPI, 2022)
Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; ... |
Artículo
Methodology for Distributed-ROM-based Implementation of Finite State Machines
(Institute of Electrical and Electronics Engineers, 2020)
This brief explores the optimization of distributed-ROM-based Finite State Machine (FSM) implementations as an alternative ... |
Artículo
 High-Performance Architecture for Binary-Tree-Based Finite State Machines
(IEEE Computer Society, 2018)
A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph ... |
Patente
Reconocedor reconfigurable de patrones de bits basado en jerarquía de memoria
(Oficina Española de Patentes y Marcas , 2016)
Reconocedor reconfigurable de patrones de bits basado en jerarquía de memoria que comprende una pluralidad de circuitos ... |
Tesis Doctoral
Máquinas de estados finitos con multiplexión de entradas: una contribución al diseño e implementación electrónica de máquinas de estados
(2016)
Esta tesis doctoral supone una contribución a la implementación electrónica de máquinas de estados finitos, en particular ... |
Artículo
Minimum maximum reconfiguration cost problem
(Springer, 2016)
This paper discusses the problem of minimizing the reconfiguration cost of some types of reconfigurable systems. A formal ... |
Artículo
Finite State Machines With Input Multiplexing: A Performance Study
(IEEE Computer Society, 2015)
Finite state machines with input multiplexing (FSMIMs) have been proposed in previous works as a technique for efficient mapping ... |
Artículo
The minimum maximal k-partial-matching problem
(Springer, 2013)
In this paper, we introduce a new problem related to bipartite graphs called minimum maximal k-partial-matching (MMKPM) ... |
Artículo
Finite Virtual State Machines
(Institute of Electronics, Information and Communication Engineers, 2012)
This letter proposes a new model of state machine called Finite Virtual State Machine (FVSM). A memory-based architecture ... |
Ponencia
Performance Evaluation of RAM-Based Implementation of Finite State Machines in FPGAs
(IEEE Computer Society, 2012)
This paper presents a study of performance of RAM-based implementations in FPGAs of Finite State Machines (FSMs). The ... |
Ponencia
ROM-Based Finite State Machine Implementation in Low Cost FPGAs
(IEE, 2007)
This work presents a technique for the resource optimization of input multiplexed ROM-based Finite State Machines. This ... |
Ponencia
FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration
(IEEE Computer Society, 2007)
In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations ... |
Ponencia
Propuesta para la elaboración de prácticas de codiseño de bajo coste
(Universidad Politécnica de Madrid, 2006)
En esta comunicación se presenta una propuesta para la elaboración de prácticas de sistemas digitales basados en codiseño. ... |
Artículo
ROM-based FSM implementation using input multiplexing in FPGA devices
(IET Digital Library, 2004)
A new approach for ROM implementation of finite state machines (FSMs) is proposed, based on the selection of a subset of ... |
Ponencia
Synthetic generation of address-events for real-time image processing
(IEEE Computer Society, 2003)
Address-event-representation (AER) is a communication protocol that emulates the nervous system's neurons communication, ... |
Artículo
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing ... |
Ponencia
An algorithm for numerical reference generation in symbolic analysis of large analog circuits
(Institute of Electrical and Electronics Engineers, 1997)
This paper addresses the problems arising in the calculation of numerical references (network function coefficients), ... |
Ponencia
SIRENA: A simulation environment for CNNs
(Institute of Electrical and Electronics Engineers, 1994)
SIRENA is a general simulation environment for artificial neural networks, with emphasis towards CNNs. A special interest ... |