FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration

Senhadji Navarro, Raouf; García Vargas, Ignacio; Jiménez Moreno, Gabriel; Civit Balcells, Antón

doi:10.1109/ICECS.2007.4510959

Ponencia

dc.creator	Senhadji Navarro, Raouf	es
dc.creator	García Vargas, Ignacio	es
dc.creator	Jiménez Moreno, Gabriel	es
dc.creator	Civit Balcells, Antón	es
dc.date.accessioned	2019-12-10T09:34:36Z
dc.date.available	2019-12-10T09:34:36Z
dc.date.issued	2007
dc.identifier.citation	Senhadji Navarro, R., García Vargas, I., Jiménez Moreno, G. y Civit Balcells, A. (2007). FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration. En ICECS 2007: 14th IEEE International Conference on Electronics, Circuits and Systems (178-181), Marrakech, Morocco: IEEE Computer Society.
dc.identifier.isbn	978-1-4244-1377-5	es
dc.identifier.uri	https://hdl.handle.net/11441/90787
dc.description.abstract	In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA. The proposed RAM specification has been tested with different target devices.	es
dc.description.sponsorship	Ministerio de Educación y Ciencia TEC2006-11730-C03-02	es
dc.format	application/pdf	es
dc.language.iso	eng	es
dc.publisher	IEEE Computer Society	es
dc.relation.ispartof	ICECS 2007: 14th IEEE International Conference on Electronics, Circuits and Systems (2007), p 178-181
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.title	FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration	es
dc.type	info:eu-repo/semantics/conferenceObject	es
dcterms.identifier	https://ror.org/03yxnpp24
dc.type.version	info:eu-repo/semantics/submittedVersion	es
dc.rights.accessRights	info:eu-repo/semantics/openAccess	es
dc.contributor.affiliation	Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores	es
dc.relation.projectID	TEC2006-11730-C03-02	es
dc.relation.publisherversion	https://ieeexplore.ieee.org/document/4510959	es
dc.identifier.doi	10.1109/ICECS.2007.4510959	es
dc.contributor.group	Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación
idus.format.extent	4	es
dc.publication.initialPage	178	es
dc.publication.endPage	181	es
dc.eventtitle	ICECS 2007: 14th IEEE International Conference on Electronics, Circuits and Systems	es
dc.eventinstitution	Marrakech, Morocco	es
dc.relation.publicationplace	New York, USA	es

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