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Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits

 

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Opened Access Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits
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Author: Guerrero Martos, David
Wilke, G.
Güntzel, J.L.
Bellido Díaz, Manuel Jesús
Juan Chico, Jorge
Ruiz de Clavijo Vázquez, Paulino
Millán Calderón, Alejandro
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Date: 2003
Published in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799
ISBN/ISSN: 978-3-540-20074-1
0302-9743
Document type: Chapter of Book
Abstract: The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. A key factor in timing analysis is the election of the delay model type. Pin-to-pin delay models are usually employed, but their application is limited in timing analysis when dealing with floating mode or complex gates. This paper does not introduce a delay model but a delay model type called Transistor Path Delay Model (TPDM). This new type of delay model is specially useful for timing analysis in floating mode, since it is not required to know the whole input sequence to apply it, and can manage complex CMOS gates. An algorithm to get upper bounds on the stabilization time of each gate output using TPDM is also introduced.
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Format: PDF

URI: http://hdl.handle.net/11441/52513

DOI: 10.1007/978-3-540-39762-5_56

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