dc.creator | Guerrero Martos, David | es |
dc.creator | Wilke, G. | es |
dc.creator | Güntzel, J.L. | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Millán Calderón, Alejandro | es |
dc.date.accessioned | 2017-01-20T09:14:02Z | |
dc.date.available | 2017-01-20T09:14:02Z | |
dc.date.issued | 2003 | |
dc.identifier.citation | Guerrero Martos, D., Wilke, G.,...,Millán Calderón, A. (2003). Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. En Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799 (pp. 501-510). Berlin: Springer. | |
dc.identifier.isbn | 978-3-540-20074-1 | es |
dc.identifier.issn | 0302-9743 | es |
dc.identifier.uri | http://hdl.handle.net/11441/52513 | |
dc.description.abstract | The verification of the timing requirements of large VLSI
circuits is generally performed by using simulation or timing analysis on
each combinational block of the circuit. A key factor in timing analysis is
the election of the delay model type. Pin-to-pin delay models are usually
employed, but their application is limited in timing analysis when dealing
with floating mode or complex gates. This paper does not introduce a
delay model but a delay model type called Transistor Path Delay Model
(TPDM). This new type of delay model is specially useful for timing
analysis in floating mode, since it is not required to know the whole
input sequence to apply it, and can manage complex CMOS gates. An
algorithm to get upper bounds on the stabilization time of each gate
output using TPDM is also introduced. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Springer | es |
dc.relation.ispartof | Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799 | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits | es |
dc.type | info:eu-repo/semantics/bookPart | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.publisherversion | http://link.springer.com/chapter/10.1007%2F978-3-540-39762-5_56 | es |
dc.identifier.doi | 10.1007/978-3-540-39762-5_56 | es |
idus.format.extent | 10 | es |
dc.publication.initialPage | 501 | es |
dc.publication.endPage | 510 | es |
dc.relation.publicationplace | Berlin | es |